PIC32MX440F256H-80I Datasheet, PDF (43/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
2.3.1 FIXED MAPPING TRANSLATION
The PIC32MX3XX/4XX Family core provides a simple
Fixed Mapping Translation (FMT) mechanism that is
smaller and simpler than a full Translation Lookaside
Buffer (TLB) found in other MIPS cores. Like a TLB, the
FMT performs virtual-to-physical address translation
and provides attributes for the different segments.
Those segments that are unmapped in a TLB
implementation (kseg0 and kseg1) are translated
identically by the FMT. Figure 2-3 shows how the FMT
is implemented in the PIC32MX core.
FIGURE 2-3:
ADDRESS TRANSLATION DURING MEMORY ACCESS
Instruction
Address
Calculator
Virtual
Address
Physical
Address
FMT
SRAM
Interface
Data
Address
Calculator
Virtual
Address
Physical
Address
Instn
SRAM
Data
SRAM
In general, the FMT also determines the cacheability of
each segment. These attributes are controlled via bits
in the Config register. Table 2-4 shows the encoding for
the K23 (bits 30:28), KU (bits 27:25), and K0 (bits 2:0)
fields of the Config register. The PIC32MX core passes
these Config fields to the Prefetch Cache module to
determine cacheability of Program Memory Flash
accesses. Table 2-5 shows how the cacheability of the
virtual address segments is controlled by these fields.
TABLE 2-4: CACHE COHERENCY
ATTRIBUTES
Config Register
Fields
K23, KU, and K0
Cache Coherency Attribute
2
Uncached
3
Cacheable
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 41