PIC32MX440F256H-80I Datasheet, PDF (203/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
TABLE 10-5: DMA CHANNEL 0 INTERRUPT REGISTER SUMMARY⁽¹⁾
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1070
IEC1
23:16
—
—
—
—
DMA3IE DMA2IE DMA1IE DMA0IE
BF88_1040
IFS1
23:16
—
—
—
—
DMA3IF DMA2IF DMA1IF DMA0IF
BF88_1120
IPC9
7:0
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the DMA peripheral. Refer to the PIC32MX Family Reference
Manual (DS61132) for a detailed description of these registers.
TABLE 10-6: DMA CHANNEL 1 SFR SUMMARY
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3120
BF88_3124
BF88_3128
BF88_312C
BF88_3130
DCH1CON
DCH1CONCLR
DCH1CONSET
DCH1CONINV
DCH1ECON
31:24
23:16
15:8
7:0
31:0
31:0
31:0
31:24
23:16
15:8
7:0
—
—
—
CHEN
—
CFORCE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI<1:0>
Write clears selected bits in DCH1CON, read yields undefined value
Write sets selected bits in DCH1CON, read yields undefined value
Write inverts selected bits in DCH1CON, read yields undefined value
—
—
—
—
—
—
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CABORT
PATEN
SIRQEN AIRQEN
-
—
—
BF88_3134 DCH1ECONCLR 31:0
Write clears selected bits in DCH1ECON, read yields undefined value
BF88_3138 DCH1ECONSET 31:0
Write sets selected bits in DCH1ECON, read yields undefined value
BF88_313C DCH1ECONINV 31:0
Write inverts selected bits in DCH1ECON, read yields undefined value
BF88_3140 DCH1INT 31:24
—
—
—
—
—
—
—
23:16 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE
15:8
—
—
—
—
—
—
—
7:0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF
BF88_3144 DCH1INTCLR 31:0
Write clears selected bits in DCH1INT, read yields undefined value
BF88_3148 DCH1INTSET 31:0
Write sets selected bits in DCH1INT, read yields undefined value
BF88_314C DCH1INTINV 31:0
Write inverts selected bits in DCH1INT, read yields undefined value
BF88_3150 DCH1SSA 31:24
CHSSA<31:24>
23:16
CHSSA<23:16>
15:8
CHSSA<15:8>
7:0
CHSSA<7:0>
BF88_3154 DCH1SSACLR 31:0
Write clears selected bits in DCH1SSA, read yields undefined value
BF88_3158 DCH1SSASET 31:0
Write sets selected bits in DCH1SSA, read yields undefined value
BF88_315C DCH1SSAINV 31:0
Write inverts selected bits in DCH1SSA, read yields undefined value
BF88_3160 DCH1DSA 31:24
CHDSA<31:24>
23:16
CHDSA<23:16>
15:8
CHDSA<15:8>
7:0
CHDSA<7:0>
BF88_3164 DCH1DSACLR 31:0
Write clears selected bits in DCH1DSA, read yields undefined value
BF88_3168 DCH1DSASET 31:0
Write sets selected bits in DCH1DSA, read yields undefined value
BF88_316C DCH1DSAINV 31:0
Write inverts selected bits in DCH1DSA, read yields undefined value
BF88_3170 DCH1SSIZ 31:24
—
—
—
—
—
—
—
23:16
—
—
—
—
—
—
—
15:8
—
—
—
—
—
—
—
7:0
CHSSIZ<7:0>
BF88_3174 DCH1SSIZCLR 31:0
Write clears selected bits in DCH1SSIZ, read yields undefined value
BF88_3178 DCH1SSIZSET 31:0
Write sets selected bits in DCH1SSIZ, read yields undefined value
BF88_317C DCH1SSIZINV 31:0
Write inverts selected bits in DCH1SSIZ, read yields undefined value
Note 1: The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n.
—
CHERIE
—
CHERIF
—
—
—
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 201