PIC32MX440F256H-80I Datasheet, PDF (80/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
4.2.3.0.3 Using Internal FRC Oscillator with USB
The internal 8 MHz FRC oscillator is available as a
clock source to detect any USB activity during USB
SUSPEND mode and bring the module out of the SUS-
PEND mode. To enable FRC for USB usage, the
UFRCEN bit (OSCCON<2>) must be set ‘1’ before put-
ting USB module to SUSPEND mode.
4.2.4 TWO-SPEED START-UP
Two-Speed Start-up mode can be used to reduce the
device start-up latency when using all External Crystal
POSC modes, including PLL. Two-Speed Start-up uses
the FRC clock as the SYSCLK source until the Primary
Oscillator (POSC) has stabilized. After the user
selected oscillator has stabilized, the clock source will
switch to POSC. This allows the CPU to begin running
code, at a lower speed, while the oscillator is stabiliz-
ing. When the POSC has met the start-up criteria an
automatic clock switch occurs to switch to POSC. This
mode is enabled by the device Configuration bits
FCKSM<1:0> (DEVCFG1<15:14>). Two-Speed Start-
up operates after a Power-on Reset (POR) or exit from
SLEEP. Software can determine the oscillator source
currently in use by reading the COSC<2:0> bits in the
OSCCON register.
Note:
The Watchdog Timer (WDT), if enabled,
will continue to count at the same rate
regardless of the SYSCLK frequency.
Care must be taken to service the WDT
during Two-Speed Start-up, taking into
account the change in SYSCLK.
4.2.5
FAIL-SAFE CLOCK MONITOR
OPERATION
The Fail-Safe Clock Monitor (FSCM) is designed to
allow continued device operation if the current oscilla-
tor fails. It is intended for use with the Primary Oscillator
(POSC) and automatically switches to the FRC oscilla-
tor if a POSC failure is detected. The switch to the Fast
Internal RC Oscillator (FRC) oscillator allows continued
device operation and the ability to retry the POSC or to
execute code appropriate for a clock failure.
The FSCM mode is controlled by the FCKSM<1:0> bits
in the device Configuration register, DEVCFG1. Any of
the POSC modes can be used with FSCM.
When a clock failure is detected with FSCM enabled
and the FSCM Interrupt Enable bit FSCMIE
(IEC1<14>) set, the clock source will be switched from
POSC to FRC. An Oscillator Fail interrupt will be gen-
erated, with the CF bit (OSCCON<3>) set. This inter-
rupt has a user-settable priority FSCMIP<2:0>
(IPC8<12:10>) and subpriority FSCMIS<1:0>
(IPC8<9:8>). The clock source will remain FRC until a
device Reset or a clock switch is performed. Failure to
enable the FSCM interrupt will not inhibit the actual
clock switch.
The FSCM module takes the following actions when
switching to the FRC oscillator:
1. The COSC bits (OSCCON<14:12>) are loaded
with ‘000’.
2. The CF OSCCON<3> bit is set to indicate the
clock failure
3. The OSWEN control bit (OSCCON<0>) is
cleared to cancel any pending clock switches.
To enable FSCM the following steps should be
performed:
1. Enable the FSCM in the device Configuration
register, DEVCFG1, by configuring the
FCKSM<1:0> bits to ‘00’.
01 = Clock Switching is enabled, FSCM is
disabled
00 = Clock Switching and FSCM are enabled
2. Select the desired mode HS, XT, or EC using
FNOSC<2:0> in DEVCFG1.
3. Select POSC as the default oscillator in the
device Configuration register, DEVCFG1 by
configuring FNOSC<2:0> = 010 without PLL or
011 with PLL.
If the PLL is to be used:
1. Select the appropriate Configuration bits for
the PLL input divider to scale the input fre-
quency to be between 4 MHz and 5 MHz
using FPLLIDIV<2:0> (DEVCFG2<2:0>).
Note:
When using FRCPLL mode, the PLL input
divider is forced to ‘2’ to provide a 4 MHz
input to the PLL. This parameter cannot be
modified.
2. Select the desired PLL multiplier using FPLL-
MULT<2:0> (DEVCFG2<6:4>).
3. Select the desired PLL output divider using
FPLLODIV<2:0> (DEVCFG2<18:16>).
If a FSCM interrupt is desired when a FSCM event
occurs, the following steps should be performed during
start-up code:
1. Clear the FSCM interrupt bit FSCMIF
(IFS1<14>).
2. Set the Interrupt priority FSCMIP<2:0>
(IPC8<12:10>) and subpriority FSCMIS<1:0>
(IPC8<9:8>).
3. Set the FSCM Interrupt Enable bit FSCMIE
(IEC1<14>)
Note:
The Watchdog Timer, if enabled, will con-
tinue to count at the same rate regardless
of the SYSCLK frequency. Care must be
taken to service the WDT after a Fail-Safe
Clock Monitor event, taking into account
the change in SYSCLK.
DS61143E-page 78
Preliminary
© 2008 Microchip Technology Inc.