PIC32MX440F256H-80I Datasheet, PDF (334/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
13.3 Modes of Operation
The 16-bit Timer1 peripheral can operate as a
synchronous timer using internal or external clock
sources, or as a gated timer using internal clock source
and external clock pin, or as an asynchronous timer
using an external asynchronous clock source, such as
the low-power secondary oscillator. Each mode is
easily configured and described in the following
sections.
13.3.1 CONSIDERATIONS FOR ALL
TIMER 1 MODES
• Timer1 module is disabled and powered off when
the ON bit (T1CON<15>) = 0, thus providing max-
imum power savings. All other TxCON bits
remain unchanged.
• Updates to the T1CON register should only be
performed when the timer module is disabled, ON
bit (T1CON<15>) = 0.
• Timer1 continues operating when the CPU goes
into Idle mode if the “Stop In Idle mode” control bit
is disabled, SIDL (TxCON<13>) bit = 0. If
enabled, SIDL = 1, the timer module stops
operation while the CPU is in Idle mode.
• Setting or clearing the ON bit (T1CON<15>) and
any other bits in T1CON in the same instruction
may cause undefined behavior. The user is
advised to program the T1CON register with the
desired settings with one instruction, and then set
the ON bit in a subsequent instruction.
13.3.2 SYNCHRONOUS INTERNAL TIMER
In this mode, the timer clock source is the internal
PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0.
Clock synchronization is not required, therefore the
Timer1 Synchronization bit, TSYNC (T1CON<2>), is
ignored. The TMR1 Count register increments on every
PBCLK clock cycle when the timer clock prescale
<TCKPS> is 1:1.
Timer1 generates a timer match event after the TMR1
Count register matches the PR1 Period register value
(mid-clock cycle on the falling edge), then resets to
0x0000 on the next PBCLK clock cycle. See
Section 13.5 “Timer Interrupts” regarding timer
events and interrupts.
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = PBCLK/N and the TMRx Count
register increments on every Nth PBCLK clock. For
further details regarding the timer prescaler, refer to
Section 13.4.2 “Timer Clock Prescaler”.
The following steps should be performed to properly
configure the Timer1 peripheral for Timer mode
operation.
1. Clear ON control bit (T1CON<15>) = 0 to
disable timer.
2. Configure TCKPS control bits (T1CON<5:4) to
select desired timer clock prescale.
3. Set TCS control bit (T1CON<1>) = 0 to select
the internal PBCLK clock source.
4. Clear TMR1 register.
5. Load PR1 register with desired 16-bit match
value.
6. If timer interrupts are to be used, refer to
Section 13.5 “Timer Interrupts” for interrupt
configuration steps.
7. Set ON control bit = 1 to enable Timer.
EXAMPLE 13-1:
T1CON = 0x0
SYNCHRONOUS
INTERNAL TIMER
INITIALIZATION
// Stop and Init Timer
TMR1 = 0x0;
// Clear timer register
PR1 = 0xFFFF;
// Load period register
T1CONSET = 0x8000;// Start Timer
DS61143E-page 332
Preliminary
© 2008 Microchip Technology Inc.