PIC32MX440F256H-80I Datasheet, PDF (413/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

18.5 I²C Module Addresses
The I2CxADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CxCON<10>) is ‘0’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 Least
Significant bits of the I2CxADD register.
If the A10M bit is ‘1’, the address is assumed to be a
10-bit address. When the first address byte is received,
it will be compared with the binary value, ‘11110 A9
A8 R/W = 0 (where A9 and A8 are Most Significant bits
of the 10-bit address stored in I2CxADD). If that value
matches, the next address byte will be compared with
the Least Significant 8 bits of I2CxADD, as specified in
the 10-bit addressing protocol.
TABLE 18-1:
0x00
0x01-0x03
0x04-0x07
0x08-0x77
0x78-0x7b
0x7c-0x7f
7-BIT I²C™ SLAVE
ADDRESSES SUPPORTED BY
PIC32MX3XX/4XX
General call address or Start byte
Reserved
Hs mode Master codes
Valid 7-bit addresses
10-bit address upper byte
Reserved
18.6 Slave Address Masking
The I2CxMSK register (Register 18-4) designates
address bit positions as “don’t care” (= 1) for both 7-bit
and 10-bit Addressing modes. Setting a particular bit
location (= 1) in the I2CxMSK register, causes the slave
module to respond, whether the corresponding
address bit value is a ‘0’ or ‘1’. For example, when
I2CxMSK is set to ‘00110000’, the slave module will
detect both addresses, ‘0000000’ and ‘00100000’.
18.7 Strict Addressing Support
The control bit, STRICT, enables the module to support
the strict addressing. It enables the module to enforce
all reserved addresses if they fall within the reserved
address table. If the user wants to enforce the reserved
address space, the STRICT (I2CxCON<11>) bit must
be set to ‘1’. Once the bit is set, the device will not
acknowledge reserved addresses, regardless of the
address mask settings.
PIC32MX3XX/4XX
18.8 General Call Address Support
The general call address is used to address all devices.
When this address is used, all devices should, in
theory, respond with an Acknowledgement.
The general call address is one of eight addresses
reserved for specific purposes by the I²C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the General
Call Enable (GCEN) bit is set (I2CxCON<7> = 1). When
the interrupt is serviced, the source for the interrupt can
be checked by reading the contents of the I2CxRCV to
determine if the address was device-specific or a general
call address. Upon detection of general call address,
GCSTAT (I2CxSTAT<9>) bit is set. This method is
available in both 7-bit and 10-bit Addressing modes.
18.9 Automatic Clock Stretch
In Slave modes, the module can synchronize buffer
reads and writes to the master device by clock
stretching.
18.9.1 TRANSMIT CLOCK STRETCHING
Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared,
indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
performed, irrespective of the STREN bit. The user’s
ISR must set the SCLREL bit before transmission is
allowed to continue. By holding the SCLx line low, the
user has time to service the ISR and load the contents
of the I2CxTRN before the master device can initiate
another transmit sequence.
18.9.2 RECEIVE CLOCK STRETCHING
The STREN bit in the I2CxCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCLx pin will be held low at
the end of each data receive sequence.
The user’s ISR must set the SCLREL bit before recep-
tion is allowed to continue. By holding the SCLx line
low, the user has time to service the ISR and read the
contents of the I2CxRCV before the master device can
initiate another receive sequence. This will prevent buf-
fer overruns from occurring.
18.10 Software Controlled Clock
Stretching (STREN = 1)
When the STREN bit is ‘1’, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching.
If the STREN bit is ‘0’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 411