PIC32MX440F256H-80I Datasheet, PDF (40/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events, or program errors. Table 2-3
shows the exception types in order of priority.
TABLE 2-3: PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES
Exception
Description
Reset
DSS
DINT
NMI
Assertion MCLR or a Power-On Reset (POR)
EJTAG Debug Single Step
EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the
EjtagBrk bit in the ECR register
Assertion of NMI signal
Interrupt
DIB
AdEL
IBE
DBp
Assertion of unmasked hardware or software interrupt signal
EJTAG debug hardware instruction break matched
Fetch address alignment error
Fetch reference to protected address
Instruction fetch bus error
EJTAG Breakpoint (execution of SDBBP instruction)
Sys
Bp
RI
CpU
CEU
Ov
Tr
DDBL / DDBS
AdEL
AdES
Execution of SYSCALL instruction
Execution of BREAK instruction
Execution of a Reserved Instruction
Execution of a coprocessor instruction for a coprocessor that is not enabled
Execution of a CorExtend instruction when CorExtend is not enabled
Execution of an arithmetic instruction that overflowed
Execution of a trap (when trap condition is true)
EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)
Load address alignment error
Load reference to protected address
Store address alignment error
Store to protected address
DBE
DDBL
Load or store bus error
EJTAG data hardware breakpoint matched in load data compare
DS61143E-page 38
Preliminary
© 2008 Microchip Technology Inc.