PIC32MX440F256H-80I Datasheet, PDF (484/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
21.3.4 INDEFINITE ALARM
An indefinite alarm can be generated by configuring the
CHIME bit (RTCALRM<14>) = 1; ARPT can be any
value. Once the alarm is enabled and an alarm event
occurs, the ARPT count is decremented by one. ARPT
rolls over from 0x00 to 0xFF and continues to decre-
ment on each alarm event indefinitely. The ALRMEN bit
is never automatically cleared in hardware. The user
must clear this bit to disable the indefinite alarm.
Note: An alarm event is generated when the
ARPT are = 0x00.
It is recommended to read and verify the Alarm Sync
bit, ALRMSYNC (RTCALRM<12>) = 0, before
performing the following configuration:
• Disable alarm – ALRMEN (RTCALRM<15>) = 0.
• Enable chime – CHIME (RTCALRM<14>) = 1.
• Configure alarm repeat counter – ARPT
(RTCALRM<7:0>) = 0 to 256.
• Configure alarm date and time – Load
ALRMDATE and ALRMTIME registers with the
desired alarm date/time values.
• Configure mask – Load the desired AMASK
value.
• Enable Alarm – ALRMEN (RTCALRM<15>) = 0.
Refer to Example 21-6.
EXAMPLE 21-6:
CONFIGURING THE RTCC FOR INDEFINITE ALARM
/*
The following code example will update the RTCC indefinite alarm.
Assumes the interrupts are disabled.
*/
unsigned long alTime=0x23352300; // set time to 23hr, 35 min, 23 sec
unsigned long alDate=0x06111301; // set date to Monday 13 Nov 2006
while(RTCALRM&0x1000);
RTCALRMCLR=0xCFFF;
ALRMTIME=alTime;
ALRMDATE=alDate;
RTCALRMSET=0xC600;
// turn off the alarm, chime and alarm repeats; clear
// the alarm mask
// wait ALRMSYNC to be off
// clear ALRMEN, CHIME, AMASK, ARPT;
// update the alarm time and date
// re-enable the alarm, set alarm mask at once per
// hour, enable CHIME
21.4 RTCC Clock Source
The RTCC module is intended to be clocked by an
external Real-Time Clock crystal that is oscillating at
32.768 kHz. To allow the RTCC to be clocked by an
external 32.768 kHz crystal, the SOSCEN bit
(OSCCON<1>) must be set (see Section 4.0 “Oscilla-
tors”) or the FSOSCEN (DEVCFG1<5>) Configuration
bit must be programmed to ‘1’. This is the only bit
outside of the RTCC module with which the user must
be concerned of for enabling the RTCC. The status bit,
SOSCRDY (OSCCON<22>), can be used to check that
the secondary oscillator is running.
Note:
The RTCC does not have an exclusive
access to use the SOSC oscillator. This
oscillator may be used by other peripher-
als, such as the CPU as a low-power clock
source or Timer1. Refer to the
“PIC32MX3XX/4XX Reference Manual”
(DS61132) regarding the operation of the
Secondary Low-Power Oscillator.
DS61143E-page 482
Preliminary
© 2008 Microchip Technology Inc.