PIC32MX440F256H-80I Datasheet, PDF (72/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
4.2.1
SYSTEM CLOCK (SYSCLK)
GENERATION
The SYSCLK is the primary clock used by the CPU and
select peripherals such as DMA, Interrupt Controller,
and Prefetch Cache. The SYSCLK is derived from one
of the four clock sources: POSC, SOSC, FRC, or
LPRC. Some of the clock sources have specific clock
multipliers and/or divider options. No clock scaling is
applied other than the user specified values. The
SYSCLK source is selected by the device configuration
and can be changed by software during operation. The
ability to switch clock sources during operation allows
the application to reduce power consumption by reduc-
ing the clock speed. Refer to Table 4-5 for a list of SYS-
CLK sources.
TABLE 4-5: CLOCK SELECTION CONFIGURATION BIT VALUES
Oscillator Mode
Oscillator
Source
POSCMD<1:0>
FNOSC2:
FNOSC0
Notes
Fast RC Oscillator with Postscaler (FRCDIV)
Internal
xx
111
1, 2
Fast RC Oscillator divided by 16 (FRCDIV16)
Internal
xx
110
1
Low-Power RC Oscillator (LPRC)
Internal
xx
101
1
Secondary (Timer1/RTCC) Oscillator (SOSC) Secondary
xx
100
1
Primary Oscillator (HS) with PLL Module
Primary
10
011
3
(HSPLL)
Primary Oscillator (XT) with PLL Module
Primary
01
011
3
(XTPLL)
Primary Oscillator (EC) with PLL Module
Primary
00
011
3
(ECPLL)
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
Fast RC Oscillator with PLL Module
(FRCPLL)
Internal
10
001
1,4
Fast RC Oscillator (FRC)
Internal
xx
000
1
Note 1: OSCO pin function as PBCLK out or Digital I/O is determined by the OSCIOFNC Configuration bit. When
the pin is not required by the Oscillator mode it may be configured for one of these noted options.
2: Default Oscillator mode for an unprogrammed (erased) device.
3: When using the PLL modes the input divider must be chosen such that resulting frequency applied to the
PLL is in the range of 4 MHz to 5 MHz.
4: In this mode, the PLL input divider is forced to ‘2’ to provide a 4 MHz input to the PLL. This parameter
cannot be modified and satisfies the requirements described in Note 3.
DS61143E-page 70
Preliminary
© 2008 Microchip Technology Inc.