PIC32MX440F256H-80I Datasheet, PDF (176/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 8-8:
PROLOGUE WITH A
DEDICATED GENERAL
PURPOSE REGISTER SET
IN ASSEMBLY CODE
rdpgpr sp, sp
mfc0 k0, Cause
mfc0 k1, EPC
srl k0, k0, 0xa
addiu sp, sp, -76
sw
k1, 0(sp)
mfc0 k1, Status
sw
k1, 4(sp)
ins k1, k0, 10, 6
ins k1,zero, 1, 4
mtc0 k1, Status
addu s8, sp, zero
// start interrupt handler code here
8.6.2.2 Multi-Vector Mode Epilogue
After completing all useful code of the interrupt handler
routine, the original state of the Status and ErrorEPC
registers, along with the General Purpose Registers
saved on the stack, must be restored. (The Status and
ErrorEPC registers are located in the CPU; refer to
Section 2.0 "PIC32MX MCU" of this manual for more
information.)
EXAMPLE 8-9:
EPILOGUE WITHOUT A
DEDICATED GENERAL
PURPOSE REGISTER SET
IN ASSEMBLY CODE
// end of interrupt handler code
addu
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
di
lw
mtc0
lw
mtc0
eret
sp, s8, zero
t9, 72(sp)
t8, 68(sp)
t7, 64(sp)
t6, 60(sp)
t5, 56(sp)
t4, 52(sp)
t3, 48(sp)
t2, 44(sp)
t1, 40(sp)
t0, 36(sp)
v1, 32(sp)
v0, 28(sp)
a3, 24(sp)
a2, 20(sp)
a1, 16(sp)
a0, 12(sp)
s8, 8(sp)
k0, 0(sp)
k0, EPC
k0, 4(sp)
k0, Status
EXAMPLE 8-10:
EPILOGUE WITH A
DEDICATED GENERAL
PURPOSE REGISTER SET
IN ASSEMBLY CODE
// end of interrupt handler code
addu
di
lw
mtc0
lw
mtc0
eret
sp, s8, zero
k0, 0(sp)
k0, EPC
k0, 4(sp)
k0, Status
DS61143E-page 174
Preliminary
© 2008 Microchip Technology Inc.