PIC32MX440F256H-80I Datasheet, PDF (380/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
16.4 Setup for Continuous Output
Pulse Generation
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume the timer
source is initially turned off, but this is not a requirement
for the module operation). For this example, Tx will
represent Timer2.
1. Determine the timer clock cycle time. Take into
account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
2. Calculate time to the rising edge of the output
pulse relative to the TMRx start value (0000h).
3. Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
4. Determine if the output compare module will be
used in 16 or 32-bit mode based on the previous
calculations.
5. Configure the timer to be used as the time base
for 16 or 32-bit mode by writing to the T32 bit
(TxCON<T32>).
6. Configure the output compare channel for 16 or
32-bit operation by writing to the OC32 bit
(OCxCON<5>).
7. Write the values computed in step 2 and 3
above into the Compare register, OCxR, and the
Secondary Compare register, OCxRS,
respectively.
8. Set Timer Period register, PRx, to the value equal
to or greater than the value in OCxRS, the
Secondary Compare register.
9. Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OCx pin state will
now be driven low.
10. Enable the compare time base by setting the ON
(TxCON<15>) bit to ‘1’.
11. Upon the first match between TMRx and OCxR,
the OCx pin will be driven high.
12. When the compare time base, TMRy, matches
the Secondary Compare register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin.
13. As a result of the second compare match event,
the OCxIF interrupt flag bit set.
14. When the compare time base and the value in its
respective Period register match, the TMRx
register resets to 0x0000 and resumes counting.
15. Steps 8 through 11 are repeated and a continuous
stream of pulses is generated, indefinitely. The
OCxIF flag is set on each OCxRS-TMRx compare
match event.
16.5 Pulse-Width Modulation Mode
There are two modes of PWM operation for this device:
PWM and PWM with Fault input. The configuration of
both modes is identical with the exception of the value
written to the OCM bits to select the desired mode.
The following steps should be taken when configuring
the output compare module for PWM operation:
1. Calculate the PWM period.
2. Calculate the PWM duty cycle.
3. Determine if the Output Compare module will be
used in 16 or 32-bit mode based on the previous
calculations.
4. Configure the timer to be used as the time base
for 16 or 32-bit mode by writing to the T32 bit
(TxCON<T32>).
5. Configure the output compare channel for 16 or
32-bit operation by writing to the OC32 bit
(OCxCON<5>).
6. Set the PWM period by writing to the selected
Timer Period register (PR).
7. Set the PWM duty cycle by writing to the OCxRS
register.
8. Write the OCxR register with the initial duty
cycle.
9. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin
utilization.
10. Configure the output compare module for one of
two PWM operation modes by writing to the Out-
put Compare mode bits OCM<2:0>
(OCxCON<2:0>).
11. Set the TMRx prescale value and enable the
time base by setting ON (TxCON<15>) = 1.
Note:
The OCxR register should be initialized
before the output compare module is first
enabled. The OCxR register becomes a
read-only Duty Cycle register when the
module is operated in the PWM modes.
The value held in OCxR will become the
PWM duty cycle for the first PWM period.
The contents of the Duty Cycle Buffer
register, OCxRS, will not be transferred
into OCxR until a time base period match
occurs.
DS61143E-page 378
Preliminary
© 2008 Microchip Technology Inc.