PIC32MX440F256H-80I Datasheet, PDF (35/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

2.0 PIC32MX MCU
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX Family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a detailed
description of the PIC32MX mcu.
Resources for the MIPS32^® M4K^®
Processor Core are available at
www.mips.com/products/cores/32-bit-cores/
mips32-m4k/#.
The MCU module is the heart of the PIC32MX3XX/4XX
Family processor. The MCU fetches instructions,
decodes each instruction, fetches source operands,
executes each instruction and writes the results of
instruction execution to the proper destinations.
2.1 Features
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-Accumulate and Multiply-Subtract
Instructions
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- WAIT Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
• MIPS16e™ Code Compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE & RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple Dual Bus Interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
PIC32MX3XX/4XX
• Autonomous Multiply/Divide Unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 34 clock latency (dividend (rs) sign
extension-dependent)
• Power Control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace
- Support for single stepping
- Virtual instruction and data address/value
breakpoints
- PC tracing with trace compression
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 33