PIC32MX440F256H-80I Datasheet, PDF (81/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
4.2.5.1 FSCM Delay
On a POR, BOR or wake from Sleep mode event, a
nominal delay (TFSCM) may be inserted before the
FSCM begins to monitor the system clock source.
Refer to Section 5.0 “Resets” for FSCM delay timing
information.
The TFSCM interval is applied whenever the FSCM is
enabled and the HS, HSPLL, XT, XTPLL, or SOSC
Oscillator modes are selected as the system clock.
Note:
Please refer to the Electrical
Characteristics section for TFSCM
specification values.
4.2.5.2 FSCM and Slow Oscillator Start-up
A slow oscillator start-up will not generate a FSCM
event. The FSCM does not begin monitoring until the
source to be monitored is running. If the oscillator does
not start-up the device will not run due to the lack of a
clock source. To detect the failure and prevent this the
user should use Two-Speed Start-Up to allow the
device to run using the FRC oscillator while the POSC
oscillator starts up. The COSC<2:0> bits can then be
polled to test for the clock switch to POSC. Refer to
Section 4.2.4 “Two-Speed Start-up” for further infor-
mation.
4.2.5.3 FSCM and Slow Clock Sources
Use of the FSCM with slow clock sources (below 100
kHz) is not recommended. Slow clock sources may
cause the FSCM to incorrectly detect a clock failure
event.
4.2.5.4 FSCM and WDT
The FSCM and the WDT both use the LPRC oscillator
as their time base. In the event of a clock failure, the
WDT is unaffected and continues to run.
4.2.6 CLOCK SWITCHING OPERATION
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC32MX3XX/4XX devices have a
safeguard lock built into the switch process.
Note:
Primary Oscillator mode has three differ-
ent submodes (XT, HS and EC) which are
determined by the POSCMD Configura-
tion bits in DEVCFG1. While an applica-
tion can switch to and from Primary
Oscillator mode in software, it cannot
switch between the different primary sub-
modes without reprogramming the device.
Note:
The device does not prevent changing the
PLL postscaler or multiplier values on the
clock source that is in use. The device will
not permit direct switching between PLL
clock sources. The user should not
change the PLL multiplier values or post-
scaler values when running from the
affected PLL source. To perform either of
the above clock switching functions, the
clock switch should be performed in two
steps. The clock source should first be
switched to a non-PLL source, such as
FRC, and then switched to the desired
source. This requirement only applies to
PLL-based clock sources.
4.2.6.1 Enabling Clock Switching
To enable clock switching, the FCKSM1 Configuration
bit (DEVCFG1<15>) must be programmed to ‘0’. If the
FCKSM1 Configuration bit is unprogrammed (= 1), the
clock switching function and Fail-Safe Clock Monitor
function are disabled. This is the default setting.
The NOSC control bits (OSCCON<10:8>) do not con-
trol the clock selection when clock switching is dis-
abled. However, the COSC bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
4.2.6.2 Oscillator Switching Sequence
At a minimum, performing a clock switch requires the
following sequence:
1. If desired, read the COSC<2:0> bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register. The unlock sequence
has critical timing requirements and should be
performed with interrupts and DMA disabled.
3. Write the appropriate value to the NOSC<2:0>
control bits (OSCCON<10:8>) for the new
oscillator source.
4. Set the OSWEN bit (OSCCON<0>) to initiate
the oscillator switch.
5. Optionally perform the lock sequence to lock the
OSCCON. The lock sequence must be per-
formed separately from any other operation.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC<2:0> Status bits with the new value of
the NOSC control bits. If they are the same, then
the clock switch is a redundant operation. In this
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 79