PIC32MX440F256H-80I Datasheet, PDF (341/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
14.0 TIMERS 2, 3, 4, 5
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a
detailed description of this peripheral.
This family of PIC32MX devices features four
synchronous 16-bit timers (default) that can operate as
a free-running interval timer for various timing applica-
tions and counting external events. The following
modes are supported:
• Synchronous Internal 16-bit Timer
• Synchronous Internal 16-bit Gated Timer
• Synchronous External 16-bit Timer
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
• Synchronous Internal 32-bit Timer
• Synchronous Internal 32-bit Gated Timer
• Synchronous External 32-bit Timer
Note:
Throughout this chapter, references to
registers TxCON, TMRx, and PRx use ‘x’
to represent Timer2 through 5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or 4; ‘y’ represents Timer3 or 5.
14.1 Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU IDLE
• Time base for input capture and output compare
modules (Timer2 and Timer3 only)
• ADC event trigger (Timer3 only)
• Fast bit manipulation using CLR, SET and INV
registers
Table 14-1 highlights the available features of these
timers.
TABLE 14-1: TIMER FEATURES
Timers
Low-Power Asynchronous
Oscillator External Clock
16-bit
Synchronous
Timer
32-bit
Synchronous
Timer⁽¹⁾
2, 4
No
No
Yes
Yes
3, 5
No
No
Yes
Yes
Note 1: 32-bit mode requires combining timers 2 and 3 or timers 4 and 5.
2: ADC event trigger supported by Timer3 only.
Gated Timer
Yes
Yes
Special
Event
Trigger
No
Yes⁽²⁾
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 339