PIC32MX440F256H-80I Datasheet, PDF (381/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
16.5.1 PWM WITH FAULT PROTECTION
INPUT PIN
When the Output Compare mode bits, OCM<2:0>
(OCxCON<2:0>), are set to ‘111’, the selected output
compare channel is configured for the PWM mode of
operation. All functions of the PWM are applicable with
the addition of Fault Protection Input.
Fault protection is provided via the OCFA and OCFB
pins. The OCFA pin is associated with output compare
channels 1 through 4, while the OCFB pin is associated
with output compare channel 5.
If a logic ‘0’ is detected on the OCFA/OCFB pin, the
selected PWM output pin(s) is placed in a high-
impedance state. The user may elect to provide a pull-
down or pull-up resistor on the PWM pin to provide a
desired state if a Fault condition occurs. The shutdown
of the PWM output is immediate and is not tied to the
device clock source. This state will remain until the
following changes occur:
• the external Fault condition has been removed
• PWM mode is re-enabled by writing to the mode
bits OCM<2:0>.
As a result of the Fault condition, the respective inter-
rupt flag OCxIF is asserted and an interrupt will be gen-
erated, if it is enabled. Upon detection of the Fault
condition, the OCFLT bit (OCxCON<4>) is asserted
high (logic ‘1’). This bit is a read-only bit and will only be
cleared once the external Fault condition has been
removed and the PWM mode is re-enabled, by writing
to the appropriate mode bits, OCM<2:0>.
16.5.2 PWM PERIOD
The PWM period is specified by writing to PR, the
Timer Period register. The PWM period can be
calculated using Equation 16-1.
EQUATION 16-1: CALCULATING THE PWM
PERIOD
PWM Period = [(PR+ 1) • TPB • (TMR Prescale Value)]
PWM Frequency = 1/[PWM Period]
Note:
A PRy value of N will produce a PWM
period of N + 1 time base count cycles. For
example, a value of 7 written into the PRy
register will yield a period consisting of
8 time base cycles.
16.5.3 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
OCxRS register. The OCxRS register can be written to
at any time, but the duty cycle value is not latched into
OCxR until a match between the PR and timer occurs
(i.e., the period is complete). This provides a double
buffer for the PWM duty cycle and is essential for glitch-
less PWM operation. In the PWM mode, OCxR is a
read-only register.
Some important boundary parameters of the PWM duty
cycle include:
• If the Duty Cycle register, OCxR, is loaded with
0000h, the OCx pin will remain low (0% duty cycle).
• If OCxR is greater than PR (Timer Period register),
the pin will remain high (100% duty cycle).
• If OCxR is equal to PR, the OCx pin will be low for
one time base count value and high for all other
count values.
See Example 16-2 for PWM mode timing details.
Table shows example PWM frequencies and
resolutions for a device peripheral bus operating at
10 MHz.
EQUATION 16-2: CALCULATION FOR MAXIMUM PWM RESOLUTION
( ) ^log10
FPB
FPWM • TMRy • Prescaler
Maximum PWM Resolution (bits) =
bits
log₁₀(2)
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 379