PIC32MX440F256H-80I Datasheet, PDF (453/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

20.2 Modes Of Operation
20.2.1 CONSIDERATIONS FOR PMP
MODULE
• The PMP module is enabled and ready when the
ON bit (PMCON<15>) is set = 1, therefore it is
recommended to configure the desired operating
mode prior to enabling the module.
• The PMP module is disabled and powered off
when the ON bit (PMPCON<15>) = 0, thus pro-
viding maximum power savings.
• It is recommended to wait for any pending read or
write operation to be completed before
enabling/disabling or re-configuring the module
20.2.2 CONSIDERATIONS FOR MASTER
MODES
• Setting address bits A15 and A14 = 1 when
PMCS2 and PMCS1 are enabled as Chip Selects
will cause both PMCS2 and PMCS1 to be active
during a read or write operation. This may enable
two devices simultaneously and should be
avoided.
• It is always recommended to poll the PMP’s
BUSY bit prior to any read or write operation to
ensure the prior PMP operation has completed.
The PMP module offers two Master modes of operation
featuring 16-bit or 8-bit data (default), up to 16 bits of
address, and all control signals to operate a variety of
external parallel devices such as memory devices,
peripherals, and slave microcontrollers. An example
using Master Mode 2 is shown in Figure 20-2.
FIGURE 20-2:
EXAMPLE: PMP MASTER
MODE 2, PARTIAL
MULTIPLEXED
INTERFACE
PIC32MX3XX/4XX
ADRMUX<1:0> = 01
Address Bus
Multiplexed Data
and Address Bus
Data Bus
Control Lines
PMA<13:8>
PMD<7:0>
PMD<15:8>
PMA14/PMCS1
PMA15/PMCS2
PMA0/PMALL
PMRD
PMWR
PIC32MX3XX/4XX
20.2.3 MASTER MODE SELECTION
The two Master modes are selected using MODE<1:0>
bits (PMCON<9:8>). Master Mode 1 is selected by con-
figuring MODE<1:0> bits = 11; Master Mode 2 is
selected by configuring MODE<1:0> bits = 10.
20.2.4 8, 16-BIT DATA MODES
The PMP in Master mode supports data widths 8 and
16 bits wide. By default, the data width is 8-bit,
MODE16 (PMMODE<10>) bit = 0. To select 16-bit data
width, set MODE16 = 1. When configured in 8-bit Data
mode, the upper 8 bits of the data bus, PMD<15:8>, are
not controlled by the PMP module and are available as
general purpose I/O pins.
Note: On 64-pin devices, data pins PMD<15:8>
are not available.
20.2.5 CHIP SELECTS
Two Chip Select lines, PMCS1 and PMCS2, are avail-
able for the Master modes. The two Chip Select lines
are multiplexed with the Most Significant bits of the
address bus A14 and A15. If a pin is configured as a
Chip Select, it is not included in any PMA<15:0>
address auto-increment/decrement. It is possible to
enable both PMCS2 and PMCS1 as Chip Selects, or
enable only PMCS2 as a Chip Select, allowing PMCS1
to function strictly as address line A14. It is not possible
to enable only PMCS1. The Chip Select signals are
configured using the Chip Select Function bits
CSF<1:0> (PMCON <7:6>).
TABLE 20-3: CHIP SELECT CONTROL
CSF<1:0>
FUNCTION
00
PMCS2 = A15, PMCS1 = A14
01
PMCS2 = Enabled, PMCS1 = A14
10
PMCS2, PMCS1 = Enabled
Refer to Section 20.2.16 “Addressing Consider-
ations” for information regarding Chip Select address
mapping.
20.2.6 PORT PIN CONTROL
The PMAEN register controls the functionality of the
address pins PMA<15:0>. Setting any PMAEN bit = 1
configures the corresponding PMA pin as an address
line. Those bits set = 0 remain as general purpose I/O
pins.
Refer to Section 20.5 “I/O Pin Control” regarding I/O
pin configuration.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 451