PIC32MX440F256H-80I Datasheet, PDF (487/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 21-8:
RTCC INITIALIZATION WITH INTERRUPTS
/*
The following code example illustrates an RTCC initialization with interrupts enabled.
When the RTCC alarm interrupt is generated, the cpu will jump to the vector assigned to
RTCC interrupt.
*/
// assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1;
IEC1CLR=0x00008000;
// disable RTCC interrupts
RTCCONCLR=0x8000;
while(RTCCON&0x40);
// turn off the RTCC
// wait for clock to be turned off
IFS1CLR=0x00008000;
IPC8CLR=0x1f000000;
IPC8SET=0x0d000000;
IEC1SET=0x00008000;
// clear RTCC existing event
// clear the priority
// Set IPL=3, subpriority 1
// Enable RTCC interrupts
RTCTIME=0x16153300;
RTCDATE=0x06102705;
// safe to update time to 16 hr, 15 min, 33 sec
// update the date to Friday 27 Oct 2006
RTCALRMCLR=0xCFFF;
ALRMTIME=0x16154300;
ALRMDATE=0x06102705;
// clear ALRMEN, CHIME, AMASK and ARPT;
// set alarm time to 16 hr, 15 min, 43 sec
// set alarm date to Friday 27 Oct 2006
RTCALRMSET=0x8000|0x00000600; // re-enable the alarm, set alarm mask at once per day
RTCCONSET=0x8000;
while(!(RTCCON&0x40));
// turn on the RTCC
// wait for clock to be turned on
EXAMPLE 21-9: RTCC ISR
/*
The following code example demonstrates a simple interrupt service routine for RTCC
interrupts. The user’s code at this vector should perform any application specific
operations and must clear the RTCC interrupt flag before exiting.
*/
void__ISR(_RTCC_VECTOR, ipl3) __RTCCInterrupt(void)
{
// ... perform application specific operations
// in response to the interrupt
IFS1CLR=0x00008000;
}
// be sure to clear RTCC interrupt flag
// before exiting the service routine.
Note: The RTCC ISR code example shows MPLAB^® C32 C compiler specific syntax. Refer to your compiler
manual regarding support for ISRs.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 485