PIC32MX440F256H-80I Datasheet, PDF (128/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
8.1 Control Registers
Note:
Each PIC32MX device variant may have
one or more Interrupt channels. An ‘x’
used in the names of control/Status bits
and registers denotes the particular chan-
nel. Refer to the specific device data
sheets for more details.
The interrupts module consists of the following Special
Function Registers (SFRs):
• INTCON: Interrupt Control Register
INTCONCLR, INTCONSET, INTCONINV: Atomic Bit
Manipulation, Write-Only Registers for INTCON
• INTSTAT: Interrupt Status Register
INTSTATCLR, INTSTATSET, INTSTATINV: Atomic
Bit Manipulation, Write-Only Registers for INTSTAT
• IPTMR: Interrupt Proximity Timer Register
IPTMRCLR, IPTMRSET, IPTMRNINV: Atomic Bit
Manipulation, Write-Only Registers for IPTMR
• IFS0, IFS1: Interrupt Flag Status Registers
IFSxCLR, IFSxSET, IFSxINV: Atomic Bit
Manipulation, Write-Only Registers for IFSx
• IEC0, IEC1: Interrupt Enable Control Registers
IECxCLR, IECxSET, IECxINV: Atomic Bit
Manipulation, Write-Only Registers for IECx
• IPC0 - IPC11: Interrupt Priority Control Registers
IPCxCLR, IPCxSET, IPCxINV: Atomic Bit
Manipulation, Write-Only Registers for IPCx
The following table provides a brief summary of inter-
rupts module related registers. Corresponding regis-
ters appear after the summary, followed by a detailed
description of each register.
TABLE 8-1: INTERRUPT SFR SUMMARY
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1000 INTCON 31:24
—
23:16
—
15:8
—
7:0
—
BF88_1004 INTCONCLR 31:0
BF88_1008 INTCONSET 31:0
BF88_100C INTCONINV 31:0
BF88_1010 INTSTAT 31:24
—
23:16
—
15:8
—
7:0
—
BF88_1014 INTSTATCLR 31:0
BF88_1018 INTSTATSET 31:0
BF88_101C INTSTATINV 31:0
BF88_1020 IPTMR 31:24
23:16
15:8
7:0
BF88_1024 IPTMRCLR 31:0
BF88_1028 IPTMRSET 31:0
BF88_102C IPTMRINV 31:0
BF88_1030
IFS0
31:24 I2C1MIF
23:16 SPI1EIF
15:8 INT3IF
7:0 INT1IF
BF88_1034 IFS0CLR 31:0
BF88_1038 IFS0SET 31:0
BF88_103C IFS0INV 31:0
—
—
—
—
—
—
—
—
—
—
—
—
FRZ
—
MVEC
—
TPC<2:0>
—
—
INT4EP INT3EP INT2EP INT1EP
Write clears the selected bits in INTCON, read yields undefined value
Write sets the selected bits in INTCON, read yields undefined value
Write inverts the selected bits in INTCON, read yields undefined value
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RIPL<2:0>
—
VEC<5:0>
Write clears the selected bits in INTSTAT, read yields undefined value
Write sets the selected bits in INTSTAT, read yields undefined value
Write inverts the selected bits in INTSTAT, read yields undefined value
—
SS0
INT0EP
—
—
IPTMR<31:0>
Write clears the selected bits in IPTMR, read yields undefined value
Write clears the selected bits in IPTMR, read yields undefined value
Write clears the selected bits in IPTMR, read yields undefined value
I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF
OC5IF
IC5IF
T5IF
INT4IF OC4IF
IC4IF
T4IF
OC3IF
IC3IF
T3IF
INT2IF OC2IF
IC2IF
T2IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
Write clears the selected bits in IFS0, read yields undefined value
Write sets the selected bits in IFS0, read yields undefined value
Write inverts the selected bits in IFS0, read yields undefined value
DS61143E-page 126
Preliminary
© 2008 Microchip Technology Inc.