PIC32MX440F256H-80I Datasheet, PDF (473/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER⁽¹⁾
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
bit 16
R/W-0
ALRMEN
bit 15
R/W-0
CHIME
R/W-0
PIV
R-0
ALRMSYNC
R/W-0
R/W-0
R/W-0
AMASK<3:0>
R/W-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
ARPT<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-16
bit 15
bit 14
bit 13
bit 12
Reserved: Write ‘0’; ignore read
ALRMEN: Alarm Enable bit
1 = Alarm is enabled
0 = Alarm is disabled
Note: Hardware clears ALRMEN anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0. This field should not be written when RTCCON = 1 (RTCCON<15>) and
ALRMSYNC = 1.
CHIME: Chime Enable bit
1 = Chime is enabled – ARPT<7:0> is allowed to roll over from 00 to FF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 00
Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1.
PIV: Alarm Pulse Initial Value bit
When ALRMEN = 0, PIV is writable and determines the initial value of the alarm pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the alarm pulse.
Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1.
ALRMSYNC: Alarm Sync bit
1 = ARPT<7:0> and ALRMEN may change as a result of a half-second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since
multiple bits may be changing, which are then synchronized to the PB clock domain.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because prescaler is
> 32 RTC clock away from a half-second rollover
Note: This assumes a CPU read will execute in less than 32 PBCLKs.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 471