PIC32MX440F256H-80I Datasheet, PDF (535/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

23.7 IDLE Modes
In the IDLE modes, the CPU is halted but the System
clock (SYSCLK) source is still enabled. This allows
peripherals to continue operation when the CPU is
halted. Peripherals can be individually configured to
halt when entering IDLE by setting their respective
SIDL bit. Latency when exiting Idle mode is very low
due to the CPU oscillator source remaining active.
Notes:
Changing the PBCLK divider ratio
requires recalculation of peripheral timing.
For example, assume the UART is config-
ured for 9600 baud with a PB clock ratio of
1:1 and a POSC of 8 MHz. When the PB
clock divisor of 1:2 is used, the input fre-
quency to the baud clock is cut in half;
therefore, the baud rate is reduced to 1/2
its former value. Due to numeric truncation
in calculations (such as the baud rate divi-
sor), the actual baud rate may be a tiny
percentage different than expected. For
this reason, any timing calculation
required for a peripheral should be per-
formed with the new PB clock frequency
instead of scaling the previous value
based on a change in PB divisor ratio.
Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering
Sleep in order to save power. No oscilla-
tor start-up delay would be applied when
exiting Idle. However, when switching
back to POSC, the appropriate PLL and
or oscillator startup/lock delays would be
applied.
PIC32MX3XX/4XX
The device enters IDLE mode when the SLPEN (OSC-
CON<4>) bit is clear and a WAIT instruction is
executed.
The processor will wake or exit from IDLE mode on the
following events:
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
CPU. If the priority of the interrupt event is lower
than or equal to current priority of CPU, the CPU
will remain halted and the device will remain in
IDLE mode.
• On any source of device Reset.
• On a WDT time-out interrupt. See Section 23.10
“Wake-Up from SLEEP or IDLE on Watchdog
Time-Out (NMI)” and Section 26.0 “Watchdog
Timer”.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 533