PIC32MX440F256H-80I Datasheet, PDF (325/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

12.2.6 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, each port pin configured as a digital output
can also select between an active drive output and
open-drain output. This is controlled by the Open-Drain
Control register, ODCx, associated with each port.
From POR, when an IO pin is configured as a digital
output, its output is active drive by default. Setting a bit
in the ODCx register = 1 configures the corresponding
pin as an open-drain output.
The open-drain feature allows the generation of
outputs higher than VDD, e.g., 5V, on any desired
digital-only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification, typically 5.5v.
12.2.7 PERIPHERAL MULTIPLEXING
In many cases, I/O pins are multiplexed with more than
one peripheral. A parallel I/O port pin that is multiplexed
with a peripheral is, in general, subordinate to the
peripheral.
When a peripheral is enabled and actively driving the
multiplexed pin, the use of the pin as a general purpose
output pin is disabled. The I/O pin may be read, but the
output driver for the parallel port bit will be disabled. If,
however, a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin may be driven by a
port.
The peripheral’s output buffer data and control signals
are provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 12-2 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
In general, the dominant output control of a multiplexed
I/O pin can be determined by the order of the peripheral
output names assigned to a pin (read from left to right).
Multiplexed peripheral inputs have no priority.
For example, a pin labeled “U1TX/RF3”, indicates the
UART1 Transmit output, if enabled, has a higher prece-
dence over PORTF and therefore overrides the output
control of this pin.
PIC32MX3XX/4XX
Notes:
JTAG program/debug port is multiplexed
with PORTA pins RA0, RA1, RA4 and RA5
on 100-pin devices; PORTB pins RB10,
RB11, RB12 and RB13 on 64-pin devices.
At power-on-reset, these pins are con-
trolled by the JTAG port. To use these pins
as general purpose I/O pins, the user’s
application code must clear JTAGEN
(DDPCON<3>) bit = 0. To maintain these
pins for JTAG program/debug, the user’s
application code must maintain JTAGEN
bit = 1.
On specific 100-pin devices, the instruc-
tion TRACE port is multiplexed with
PORTA pins RA6, RA7; PORTG pins
RG12, RG13 and RG14. At Power-on
Reset, these pins are general purpose I/O
pins. To maintain these pins as general
purpose I/O pins, the user’s application
code must maintain TROEN (DDP-
CON<2>) bit = 0. To use these pins as
instruction TRACE pins, TROEN must be
set = 1.
12.2.8 SOFTWARE INPUT PIN CONTROL
Some peripheral inputs assigned to an I/O pin may not
take control of the I/O pin output driver. If the I/O pin
associated with the peripheral is configured as an out-
put, using the appropriate TRIS control bit, the user can
manually affect the state of the peripheral’s input pin
through its corresponding LAT register. This behavior
can be useful in some situations, especially for testing
purposes, when no external signal is connected to the
input pin.
In general, the following peripherals allow their input
pins to be controlled manually through the LAT
registers:
• External Interrupt pins
• Timer Clock Input pins
• Input Capture pins
• PWM Fault pins
Most serial communication peripherals, when enabled,
take full control of the I/O pin so that the input pins
associated with the peripheral cannot be affected
through the corresponding PORT registers. These
peripherals include the following modules:
• SPI
• I²C™
• UART
© 2008 Microchip Technology Inc.
Preliminary
DS61143E - page 323