PIC32MX440F256H-80I Datasheet, PDF (326/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
12.2.9 INPUT CHANGE NOTIFICATION
Certain PIC32MX I/O port pins provide Input Change
notification that can generate interrupt requests to the
processor in response to a Change-Of-State (COS) on
those selected input pins. The initial state of any
enabled Change Notice (CN) pin must be established
by reading the corresponding PORT register. This fea-
ture is capable of detecting input COS even in Sleep
mode, when the clocks are disabled. Depending on the
device pin count, there are up to 22 external signals
(CN0 through CN21) that may be selected (enabled)
for generating an interrupt request on a COS.
The following control registers are associated with the
change notice module:
• CNCON
• CNEN
• CNPUE
The CNCON control register ON bit enables or disables
the CN module and its ability to generate interrupts or
respond to mismatch conditions.
The CNEN (change notice enable) register control bits
enable each CN input. Setting any of these bits enables
a CN for the corresponding pins.
The CNPUE (change notice pull-up enable) register
control bits enable a weak pull-up to a corresponding
CN input pin. The pull-ups act as a current source that
is connected to the pin, and eliminate the need for
external resistors when push button or keypad devices
are connected.
Note:
Pull-up resistors on change notification
pins should always be disabled whenever
the port pin is configured as a digital
output.
TABLE 12-11: CHANGE NOTICE PIN AND
PULL-UP TABLE
Change Weak
Notice Pull-Up
Port Pin
64-Pin 100-Pin
Device Device
Pin#
CN0 CNPUE0 RC14
48
74
CN1 CNPUE1 RC13
47
73
CN2 CNPUE2 RB0
16
25
CN3 CNPUE3 RB1
15
24
CN4 CNPUE4 RB2
14
23
CN5 CNPUE5 RB3
13
22
CN6 CNPUE6 RB4
12
21
CN7 CNPUE7 RB5
11
20
CN8 CNPUE8 RG6
4
10
CN9 CNPUE9 RG7
5
11
CN10 CNPUE10 RG8
6
12
CN11 CNPUE11 RG9
8
14
CN12 CNPUE12 RB15
30
44
CN13 CNPUE13 RD4
52
81
CN14 CNPUE14 RD5
53
82
CN15 CNPUE15 RD6
54
83
CN16 CNPUE16 RD7
55
84
CN17 CNPUE17 RF4
31
49
CN18 CNPUE18 RF5
32
50
CN19 CNPUE19 RD13
—
80
CN20 CNPUE20 RD14
—
47
CN21 CNPUE21 RD15
—
48
12.2.10 CHANGE NOTICE INTERRUPTS
The Change Notice module is enabled as a source of
interrupts via the respective CN interrupt enable bits:
• CNIE (IEC1<0>)
• CNIF (IFS1<0>)
The interrupt priority level bits and interrupt subpriority
level bits must also be configured:
• CNIP<2:0> (IPC6<20:18>)
• CNIS<1:0> (IPC6<17:16>)
To enable CN interrupts, the ON bit (CNCON<15>)
must = 1, one or more CN input pins must be enabled
and the Change Notice Interrupt Enable bit, CNIE,
must = 1.
DS61143E - page 324
Preliminary
© 2008 Microchip Technology Inc.