PIC32MX440F256H-80I Datasheet, PDF (454/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
20.2.7 READ/WRITE CONTROL
The PMP module supports two distinct read/write sig-
naling methods. In Master Mode 1, Read and Write
strobe are combined into a single control line,
PMRD/PMWR; a second control line, PMENB, deter-
mines when a read or write action is to be taken.
In Master Mode 2, Read and Write strobes (PMRD and
PMWR) are supplied on separate pins.
To enable the PMRD/PMWR and PMWR/PMENB pins,
set PTRDEN bit (PMCON<8>) and PTWREN bit
(PMCON<9>) = 1.
20.2.8 CONTROL LINE POLARITY
All control signals (PMRD, PMWR, PMALL, PMALH,
PMCS2 and PMCS1) can be individually configured for
either positive (active-high) or negative (active-low)
polarity. The polarity for each control line is controlled
by separate bits in the PMCON register.
TABLE 20-4: MASTER MODE PIN
POLARITY
CONTROL PMCON Active-High Active-Low
PIN Control Bit Select
Select
PMRD
RDSP
1
0
PMWR
WRSP
1
0
PMCS2
CS2P
1
0
PMCS1
CS1P
1
0
PMALL/H
ALP
1
0
Note that the polarity of control signals that share the
same output pin (for example, PMWR and PMENB) are
controlled by the same bit; the configuration depends
on which Master Port mode is being used.
20.2.9 AUTO-INCREMENT/DECREMENT
While the module is operating in a Master mode, the
auto-address increment/decrement bits INCM<1:0>
(PMMODE<12:11>) control the behavior of the address
value that appears on the PMA<15:0> address pins.
The address in the PMADDR register can be made to
automatically increment or decrement by 1 (regardless
of the transfer data width) after each read and write
operation is completed, and the BUSY bit goes to ‘0’.
TABLE 20-5:
INCM<1:0>
00
01
10
ADDRESS AUTO-
INCREMENT/DECREMENT
CONFIGURATION
FUNCTION
No Increment, No Decrement
Increment every R/W Cycle
Decrement every R/W Cycle
If the Chip Select signals are disabled and configured
as address bits, the bits will participate in the increment
and decrement operations; otherwise, the PMCS2 and
PMCS1 bit values will be unaffected.
20.2.10 WAIT STATES
In Master modes, the user has control over the dura-
tion of the read, write, and address cycles by configur-
ing the module Wait states. Three portions of the
cycle, the beginning, middle, and end are configured
using the corresponding WAITB, WAITM, and WAITE
bits in the PMMODE register.
20.2.11 ADDRESS MULTIPLEXING
In either of the Master modes the address bus can be
multiplexed together with the data bus. There are three
Address Multiplexing modes available; Demultiplexed,
Partial Multiplexed and Full Multiplexed. The Address-
ing Multiplex mode is configured using bits
ADRMUX<1:0> (PMCON<12:11).
For detailed examples illustrating address multiplexing
configurations, refer to the PMP chapter in the
“PIC32MX Family Reference Manual” (DS61132).
TABLE 20-6: ADDRESS MULTIPLEX
CONFIGURATIONS
ADRMUX<1:0>
Multiplex Modes
00
Demultiplexed
01
Partial (uses PMD<7:0>)
10
Full (uses PMD<7:0>)
11
Full (uses PMD<15:0>)
Note:
A design implementing partial or full multi-
plexed address and data bus allows the
unused PMA address pins to be used as
general purpose I/O pins. However,
depending on the Multiplexing mode, read
and write operations will be extended by
several peripheral bus clock cycles,
TPBCLK.
20.2.12 DEMULTIPLEXED MODE
In Demultiplexed mode, address bits are presented on
pins PMA<15:0>. Note, PMA15 is not available if
PMCS2 is enabled and PMA14 is not available if
PMCS1 is enabled. Data bits are presented on pins
PMD<15:0> in 16-bit Data mode; pins PMD<7:0> in 8-
bit Data mode. Demultiplexed mode is selected by
configuring bits ADRMUX<1:0> = 00.
DS61143E-page 452
Preliminary
© 2008 Microchip Technology Inc.