PIC32MX440F256H-80I Datasheet, PDF (395/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 17-1: INITIALIZATION FOR 16-BIT SPI MASTER MODE
/*
The following code example will initialize the SPI1 in master mode.
It assumes that none of the SPI1 input pins are shared with an analog input.
If so, the AD1PCFG and corresponding TRIS registers have to be properly configured.
*/
int rData;
IEC0CLR=0x03800000;
SPI1CON = 0;
rData=SPI1BUF;
IFS0CLR=0x03800000;
IPC5CLR=0x1f000000;
IPC5SET=0x0d000000;
IEC0SET=0x03800000;
// disable all interrupts
// Stops and resets the SPI1.
// clears the receive buffer
// clear any existing event
// clear the priority
// Set IPL=3, subpriority 1
// Enable Rx, Tx and Error interrupts
SPI1BRG=0x1;
SPI1STATCLR=0x40;
SPI1CON=0x8220;
// use F_PB/4 clock frequency
// clear the Overflow
// SPI ON, 8 bits transfer, SMP=1, Master Mode
SPI1BUF=’A’;
// from now on, the device is ready to transmit and receive
data
// transmit an A character
17.2.3 SLAVE MODE
In Slave mode, data from the SPIxBUF register is
transmitted synchronously on the SDO (output) pin
while synchronous data is received from the Master
device on the SDI (input) pin. In this mode, the Master
device controls the synchronous data transfer with the
SCK clock pin by generating 8, 16 or 32 clock pulses,
depending on the selected data size.
17.2.3.1 Slave Mode Operations
The SDO pin is an output and the SPI pin is an input.
Setting the control bit, DISSDO (SPIxCON<12>),
disables transmission at the SDO pin if Receive Only
mode of operation is desired.
Refer to Table 17-7.
The SDI (input) must be configured to properly sample
the data received from the slave device by configuring
the sample bit, SMP (SPIxCON<9>).
Refer to timing diagram shown in Figure 17-4 to deter-
mine the appropriate settings.
Data transfers can be 8, 16, or 32 bits and are
configured using control bits. MODE<32,16>
(SPIxCON<11:10>).
Refer to Section 17.2.1 “8, 16, and 32-bit Operation”
for details.
Slave Select Synchronization: The SSx pin allows a
Synchronous Slave mode. If the SSEN (SPIxCON<7>)
bit is set, transmission and reception is enabled in
Slave mode only if the SSx pin is driven to a low state.
If the SSEN bit is not set, the SSx pin does not affect
the module operation in Slave mode.
17.2.3.2 Slave SPIxCON Configuration
The following bits must be configured as shown for the
Slave mode of operation when configuring the
SPIxCON register:
• Enable Slave Mode –
MSTEN (SPIxCON<5>) = 0.
• Disable Framed SPI support – FRMEN
(SPIxCON<31>) = 0
The remaining bits are shown with example configura-
tions and may be configured as desired:
• Enable module control of SDO pin –
DISSDO (SPIxCON<12>) = 0
• Configure SCK clock polarity to Idle high –
CKP (SPIxCON<6>) = 1
• Configure SCK clock edge transition from Idle to
active – CKE (SPIxCON<8>) = 0
• Disable Slave Select Pin –
SSEN (SPIxCON<7>) = 0
• Select 16-bit data width –
MODE<32,16> (SPIxCON<11:10>) = 01
• Sample data input at middle –
SMP (SPIxCON<9>) = 0
• Enable SPI module when CPU Idle –
SIDL (SPIxCON<13>) = 0
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 393