PIC32MX440F256H-80I Datasheet, PDF (175/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

8.6.1.2 Single Vector Mode Epilogue
After completing all useful code of the interrupt handler
routine, the original state of the Status and EPC regis-
ters, along with the General Purpose Registers saved
on the stack, must be restored.
EXAMPLE 8-6:
SINGLE VECTOR
INTERRUPT HANDLER
EPILOGUE IN ASSEMBLY
CODE
// end of interrupt handler code
addu
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
di
lw
mtc0
lw
mtc0
eret
sp, s8, zero
t9, 72(sp)
t8, 68(sp)
t7, 64(sp)
t6, 60(sp)
t5, 56(sp)
t4, 52(sp)
t3, 48(sp)
t2, 44(sp)
t1, 40(sp)
t0, 36(sp)
v1, 32(sp)
v0, 28(sp)
a3, 24(sp)
a2, 20(sp)
a1, 16(sp)
a0, 12(sp)
s8, 8(sp)
k0, 0(sp)
k0, EPC
k0, 4(sp)
k0, Status
8.6.2
INTERRUPT PROCESSING IN
MULTI-VECTOR MODE
When the interrupt controller is configured in Multi-
Vector mode, the interrupt requests are serviced at the
calculated vector addresses. The interrupt handler
routine must generate a prologue and an epilogue to
properly configure, save and restore all of the core reg-
isters, along with General Purpose Registers. At a
worst case, all of the modifiable General Purpose Reg-
isters must be saved and restored by the prologue and
epilogue. If the interrupt priority is set to receive its own
General Purpose Register set, the prologue and epi-
logue will not need to save or restore any of the modi-
fiable General Purpose Registers, thus providing the
lowest latency.
PIC32MX3XX/4XX
8.6.2.1 Multi-Vector Mode Prologue
When entering the interrupt handler routine, the Inter-
rupt Service Routine (ISR) must first save the current
priority and exception PC counter from Interrupt Priority
bits, IPL (Status<15:10>), and the ErrorEPC register,
respectively, on the stack. If the routine is presented a
new register set, the previous register set’s stack regis-
ter must be copied to the current set’s stack register.
Then, the requested priority may be stored in the IPLx
from Requested Interrupt Priority bits, RIPLx
(Cause<15:10>), Exception Level bit, EXL, and Error
Level bit, ERL, in the Status register (Status<1> and
Status<2>) are cleared, and the Master Interrupt
Enable bit (Status<0>) is set. If the interrupt handler is
not presented a new General Purpose Register set,
these resisters will be saved on the stack. (Cause and
Status are CPU registers; refer to Section 2.0
"PIC32MX MCU" of this manual for more information.)
EXAMPLE 8-7:
PROLOGUE WITHOUT A
DEDICATED GENERAL
PURPOSE REGISTER SET
IN ASSEMBLY CODE
rdpgpr sp, sp
mfc0 k0, Cause
mfc0 k1, EPC
srl k0, k0, 0xa
addiu sp, sp, -76
sw
k1, 0(sp)
mfc0 k1, Status
sw
k1, 4(sp)
ins k1, k0, 10, 6
ins k1,zero, 1, 4
mtc0 k1, Status
sw
s8, 8(sp)
sw
a0, 12(sp)
sw
a1, 16(sp)
sw
a2, 20(sp)
sw
a3, 24(sp)
sw
v0, 28(sp)
sw
v1, 32(sp)
sw
t0, 36(sp)
sw
t1, 40(sp)
sw
t2, 44(sp)
sw
t3, 48(sp)
sw
t4, 52(sp)
sw
t5, 56(sp)
sw
t6, 60(sp)
sw
t7, 64(sp)
sw
t8, 68(sp)
sw
t9, 72(sp)
addu s8, sp, zero
// start interrupt handler code here
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 173