PIC32MX440F256H-80I Datasheet, PDF (119/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 7-1: NVMCON: PROGRAMMING CONTROL REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
bit 16
R/W-0
R/W-0
R-0
R-0
R-0
r-x
r-x
r-x
NVMWR NVMWREN NVMERR LVDERR LVDSTAT
—
—
—
bit 15
bit 8
r-x
—
bit 7
r-x
r-x
r-x
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
NVMOP3 NVMOP2 NVMOP1 NVMOP0
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-16
Reserved: Write ‘0’; ignore read
bit 15
NVMWR: Write Control bit
This bit is writable when NVMWREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation (Hardware clears this bit when the operation completes.)
0 = Flash operation complete or inactive
Note: Wait at least 500 nsec after detecting a ‘0’ in NVMWR bit before writing to any NVM registers.
bit 14
NVMWREN: Write Enable bit
1 = Enables writes to NVMWR bit and enables LVD circuit
0 = Disables writes to NVMWR bit and disables LVD circuit
Note: This is the only bit in this register that is reset by a device Reset.
bit 13
NVMERR: Write Error bit
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR).
bit 12
LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)
This error is only captured for programming/erase operations
1 = Low-voltage detected
0 = Voltage level ok for programming
Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR).
bit 11
LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)
This bit is read-only and is automatically set by hardware
1 = Low-voltage event active
0 = Low-voltage event NOT active
Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR).
bit 10-4
Reserved: Write ‘0’; ignore read
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 117