PIC32MX440F256H-80I Datasheet, PDF (344/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
TABLE 14-3: TIMER3 SFR SUMMARY (CONTINUED)
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0A20 PR3 31:24
—
—
—
—
—
—
—
—
23:16
—
—
—
—
—
—
—
—
15:8
PR3<15:8>
7:0
PR3<7:0>
BF80_0A24 PR3CLR 31:0
Write clears selected bits in PR3, read yields undefined value
BF80_0A28 PR3SET 31:0
Write sets selected bits in PR3, read yields undefined value
BF80_0A2C PR3INV 31:0
Write inverts selected bits in PR3, read yields undefined value
TABLE 14-4: TIMER3 INTERRUPT REGISTER SUMMARY⁽¹⁾
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1060
BF88_1030
IEC0
IFS0
15:8 INT3IE
15:8 INT3IF
OC3IE
OC3IF
IC3IE
IC3IF
T3IE
T3IF
INT2IE
INT2IF
OC2IE
OC2IF
IC2IE
IC2IF
T2IE
T2IF
BF88_10C0 IPC3
7:0
—
—
—
T3IP<2:0>
T3IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer 3 peripheral. Refer to the PIC32MX Fam-
ily Reference Manual (DS61132) for a detailed description of these registers.
REGISTER 14-5: TIMER4 SFR SUMMARY
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
BF80_0C00 T4CON 31:24
—
—
—
—
—
—
—
23:16
15:8
7:0
BF80_0C04 T4CONCLR 31:0
—
ON
TGATE
—
—
—
—
—
—
FRZ
SIDL
—
—
—
—
TCKPS<2:0>
T32
—
TCS
Write clears selected bits in T4CON, read yields undefined value
BF80_0C08 T4CONSET 31:0
BF80_0C0C T4CONINV 31:0
BF80_0C10 TMR4 31:24
—
Write sets selected bits in T4CON, read yields undefined value
Write inverts selected bits in T4CON, read yields undefined value
—
—
—
—
—
—
23:16
—
—
—
—
—
—
—
15:8
TMR4<15:8>
7:0
TMR4<7:0>
BF80_0C14 TMR4CLR 31:0
BF80_0C18 TMR4SET 31:0
BF80_0C1C TMR4INV 31:0
BF80_0C20 PR4 31:24
—
Write clears selected bits in TMR4, read yields undefined value
Write sets selected bits in TMR4, read yields undefined value
Write inverts selected bits in TMR4, read yields undefined value
—
—
—
—
—
—
23:16
—
—
—
—
—
—
—
15:8
PR4<15:8>
7:0
PR4<7:0>
BF80_0C24 PR4CLR 31:0
BF80_0C28 PR4SET 31:0
BF80_0C2C PR4INV 31:0
Write clears selected bits in PR4, read yields undefined value
Write sets selected bits in PR4, read yields undefined value
Write inverts selected bits in PR4, read yields undefined value
Bit
24/16/8/0
—
—
—
—
—
—
—
—
REGISTER 14-6: TIMER4 INTERRUPT REGISTER SUMMARY⁽¹⁾
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1060 IEC0 23:16 SPI1EIE OC5IE
IC5IE
T5IE
INT4IE OC4IE
IC4IE
T4IE
BF88_1030 IFS0 23:16 SPI1EIF OC5IF
IC5IF
T5IF
INT4IF OC4IF
IC4IF
T4IF
BF88_10D0 IPC4
7:0
—
—
—
T4IP<2:0>
T4IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer4 peripheral. Refer to the “PIC32MX Fam-
ily Reference Manual” (DS61132) for a detailed description of these registers.
DS61143E-page 342
Preliminary
© 2008 Microchip Technology Inc.