PIC32MX440F256H-80I Datasheet, PDF (327/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
To prevent possible spurious interrupts when configur-
ing change notice interrupts, the following steps are
recommended:
1. Disable CPU interrupts.
2. Set desired CN I/O pin as input by setting corre-
sponding TRISx register bits = 1.
Note: If the I/O pin is shared with an analog
peripheral, it may be necessary to set the corre-
sponding AD1PCFG bit = 1 to ensure that the
I/O pin is a digital input.
3. Enable change notice module
ON (CNCON<15>) = 1.
4. Enable individual CN input pin(s); enable
optional pull-up(s).
5. Read corresponding PORT registers to clear
mismatch condition on CN input pins.
6. Configure the CN interrupt priority, CNIP<2:0>,
and subpriority CNIS<1:0>.
7. Clear CN interrupt flag, CNIF = 0.
8. Enable CN interrupt enable, CNIE = 1.
9. Enable CPU interrupts.
The port must be read first to clear the mismatch con-
dition, then the CN interrupt flag, CNIF (IFS1<0>), can
be cleared in software. Failing to read the port before
attempting to clear the CNIF bit may not allow the CNIF
bit to be cleared.
In addition to enabling the CN interrupt, an Interrupt
Service Routine (ISR), is required. Example 12-1 and
Example 12-2 show a partial code example of an ISR.
Note:
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
EXAMPLE 12-1: CHANGE NOTICE CONFIGURATION EXAMPLE
/*
The following code example illustrates a Change Notice
interrupt configuration for pins CN1(PORTC.RC13), CN4(PORTB.RB2) and CN18(PORTF.RF5).
*/
unsigned int value;
/* NOTE: disable vector interrupts prior to configuration */
CNCON = 0x8000;
CNEN= 0x00040012;
CNPUE= 0x00040012;
// Enable Change Notice module
// Enable CN1, CN4 and CN18 pins
// Enable weak pull ups for CN1, CN4 and CN18 pins
/* read port(s) to clear mismatch on change notice pins */
value = PORTB;
value = PORTC;
value = PORTF;
IPS6SET = 0x00140000;
IPS6SET = 0x00030000;
// Set priority level=5
// Set subpriority level=3
// Could have also done this in single
// operation by assigning IPS6SET = 0x00170000
IFS1CLR = 0x0001;
IEC1SET = 0x0001;
// Clear the interrupt flag status bit
// Enable Change Notice interrupts
/* re-enable vector interrupts after configuration */
© 2008 Microchip Technology Inc.
Preliminary
DS61143E - page 325