PIC32MX440F256H-80I Datasheet, PDF (185/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 9-3: CHETAG⁽¹⁾: CACHE TAG REGISTER
R/W-0
r-x
r-x
r-x
r-x
r-x
r-x
r-x
LTAGBOOT
—
—
—
—
—
—
—
bit 31
bit 24
R/W-x
bit 23
R/W-x
R/W-x
R/W-x
R/W-x
LTAG<23:16>
R/W-x
R/W-x
R/W-x
bit 16
R/W-x
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
LTAG<15:8>
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 7
R/W-x
R/W-x
LTAG<7:4>
R/W-x
R/W-0
LVALID
R/W-0
LLOCK
R/W-1
LTYPE
r-0
—
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31
LTAGBOOT: Line TAG Address Boot
1 = The line is in the 0x1D000000 (physical) area of memory
0 = The line is in the 0x1FC00000 (physical) area of memory
bit 30-24
Reserved: Write ‘0’; ignore read
bit 23-4
LTAG<23:4>: Line TAG Address bits
LTAG bits are compared against physical address <23:4> to determine a hit. Because its address
range and position of Flash in kernel space and user space, the LTAG Flash address is identical for
virtual addresses, (system) physical addresses, and Flash physical addresses.
bit 3
LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection
0 = The line is not valid and is not compared to the physical address for hit detection
bit 2
LLOCK: Line Lock bit
1 = The line is locked and will not be replaced
0 = The line is not locked and can be replaced
bit 1
LTYPE: Line Type bit
1 = The line caches instruction words
0 = The line caches data words
bit 0
Reserved:
Note 1: The TAG and Status of the Line pointed to by CHEIDX (CHEACC<3:0>).
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 183