PIC32MX440F256H-80I Datasheet, PDF (504/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
22.2 ADC Operation, Terminology, and
Conversion Sequence
This section will describe the operation the A/D con-
verter, the steps required to configure the converter,
describe the special feature of the module, and provide
examples of ADC configuration with timing diagrams
and charts showing the expected output of the
converter.
22.2.1 OVERVIEW OF OPERATION
Analog sampling consists of two steps: acquisition and
conversion (see Figure 22-2). During acquisition the
analog input pin is connected to the Sample and Hold
Amplifier (SHA). After the pin has been sampled for a
sufficient period, the sample voltage is equivalent to the
input, the pin is disconnected from the SHA to provide
a stable input voltage for the conversion process. The
conversion process then converts the analog sample
voltage to a binary representation.
An overview of the ADC is presented in Figure 22-1.
The 10-bit A/D converter has a single SHA. The SHA is
connected to the analog input pins via the analog input
MUXs, MUX A and MUX B. The analog input MUXs are
controlled by the AD1CHS register. There are two sets
of MUX control bits in the AD1CHS register. These two
sets of control bits allow the two different analog input
to be independently controlled. The A/D converter can
optionally switch between MUX A and MUX B configu-
rations between conversions. The A/D converter can
also optionally scan through a series of analog inputs
using a single MUX.
Acquisition time can be controlled manually or auto-
matically. The acquisition time may be started manually
by setting the SAMP bit (AD1CON1<1>), and ended
manually by clearing the SAMP in the user software.
The acquisition time may be started automatically by
the A/D converter hardware and ended automatically
by a conversion trigger source. The acquisition time is
set by the SAMC bits (AD1CON3<12:8>). The SHA
has a minimum acquisition period. Refer to the device
data sheet for acquisition time specifications
Conversion time is the time required for the A/D con-
verter to convert the voltage held by the SHA. The A/D
converter requires one ADC clock cycle (TAD) to con-
vert each bit of the result, plus two additional clock
cycles. Therefore, a total of 12 TAD cycles are required
to perform the complete conversion. When the
conversion time is complete, the result is written into
one of the 16 ADC result registers
(ADC1BUF0...ADC1BUFF).
The sum of the acquisition time and the A/D conver-
sion time provides the total sample time (refer to
Figure 22-2). There are multiple input clock options
for the A/D converter that are used to create the TAD
clock. The user must select an input clock option that
does not violate the minimum TAD specification.
The sampling process can be performed once, period-
ically, or based on a trigger as defined by the module
configuration.
FIGURE 22-2:
ADC SAMPLE/CONVERSION SEQUENCE
ADC Total Sample Time
Acquisition Time A/D Conversion Time
A/D conversion complete, result is written into the
ADC result buffer.
Optionally generate interrupt.
SHA is disconnected from input and holds the signal.
A/D conversion is started by the conversion trigger source.
SHA is connected to the analog input pin for sampling.
DS61143E-page 502
Preliminary
© 2008 Microchip Technology Inc.