PIC32MX440F256H-80I Datasheet, PDF (296/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
11.11 Enabling Host Mode and
Discovering a Connected Device
To enable Host mode, perform the following steps:
1. Enable Host mode (U1CON<HOSTEN> = 1).
This enables the D+ and D- pull-down resistors,
and disables the D+ and D- pull-up resistors. To
reduce noise on the bus, disable the SOF
packet generation by writing the SOF Enable bit
to ‘0’ (U1CON<SOFEN> = 0).
2. Enable the device attach interrupt
(U1IE<ATTACHIE> = 1).
3. Wait for the device attach interrupt
(U1IR<ATTACHIF>).
This is signaled by the USB device changing the
state of D+ or D- from ‘0’ to ‘1’ (SE0 to JSTATE).
After it occurs, wait for the device power to sta-
bilize (10 ms is minimum, 100 ms is recom-
mended).
4. Check the state of the JSTATE and SE0 bits in
the control register U1CON.
If U1CON<JSTATE> is ‘0’, the connecting
device is low speed; otherwise, the device is full
speed.
5. If the connecting device is low speed, set the
low-speed enable bit in the address register
(U1ADDR<LSPDEN>= 1), and the low-speed
bit in the Endpoint 0 Control register
(U1EP0<LSPD> = 1). But, if the device is full
speed, clear these bits.
6. Reset the USB device by sending the Reset sig-
naling for at least 50 ms (U1CON<USBRST> =
1). After 50 ms, terminate the Reset
(U1CON<USBRST> = 0).
7. Enable SOF packet generation to keep the con-
nected device from going into suspend
(U1CON<SOFEN> = 1).
8. Wait 10 ms for the device to recover from Reset.
9. Perform enumeration as described in Chapter 9
of the USB 2.0 specification.
11.11.1 HOST TRANSACTIONS
When acting as a host, a transaction consists of the fol-
lowing:
1. Software configures the appropriate BD (End-
point n, DIR, PPBI), and sets the UOWN bit to ‘1’
(HW owned).
2. Software checks the state of TOKBUSY
(U1CON<5>) to verify that any previous
transaction has completed.
3. Software writes the address of the target device
in the U1ADDR register.
4. Software writes the endpoint number and the
desired TOKEN PID (IN, OUT, or SETUP) to the
U1TOK register.
5. Hardware reads the BD to determine the appro-
priate action, and to obtain the pointer to data
memory.
6. Hardware issues the correct TOKEN PID (IN,
OUT, SETUP) on the USB link.
7. If the transaction is a transmit transaction (OUT,
SETUP), the USB module reads the packet data
out of data memory. Then the module follows
with the desired DATA PID (DATA0/DATA1) and
packet data.
8. If the transaction is a receive transaction (IN),
the USB module waits to receive the DATA PID
and packet data. Hardware writes the packet
data to memory.
9. Hardware issues or waits for a Handshake PID
(ACK, NAK, or STALL), unless the endpoint is
set up as an isochronous endpoint (EPHSHK bit
U1EPx<0> is cleared).
10. Hardware updates the BD, and writes the
UOWN bit to ‘0’ (SW owned).
11. Hardware updates the U1STAT register, and
sets the TRNIF (U1IR<3>) interrupt.
12. Hardware reads the next BD (EVEN or ODD) to
see whether it is owned by the USB module. If it
is, hardware begins the next transaction.
13. Software should read the U1STAT register, and
then clear the TRNIF interrupt.
If Software does not set the UOWN bit to ‘1’ in the
appropriate BD prior to writing the U1TOK register, the
module will read the descriptor and do nothing.
DS61143E-page 294
Preliminary
© 2008 Microchip Technology Inc.