PIC32MX440F256H-80I Datasheet, PDF (41/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

2.2.4 INTERRUPT HANDLING
The PIC32MX3XX/4XX Family core includes support
for peripheral interrupts, two software interrupts, and a
timer interrupt.
The PIC32MX MCU uses the MIPS External Interrupt
Controller (EIC) mode, which redefines the way in
which interrupts are handled to provide full support for
an external interrupt controller handling prioritization
and vectoring of interrupts. This presence of this mode
denoted by the VEIC bit in the Config3 register. On the
PIC32MX core, the VEIC bit is always set to ‘1’ to
indicate the presence of an external interrupt controller.
Note:
Although EIC mode is designated as
“External”, the interrupt controller is
on-chip.
The interrupt controller specifies which shadow set
should be used upon entry to a particular vector. The
shadow registers further improve interrupt latency by
avoiding the need to save context when invoking an
interrupt handler.
PIC32MX3XX/4XX
2.2.5 GPR SHADOW REGISTERS
Release 2 of the MIPS32 Architecture optionally
removes the need to save and restore GPRs on entry
to high priority interrupts or exceptions, and to provide
specified processor modes with the same capability.
This is done by introducing multiple copies of the
GPRs, called “shadow sets”, and allowing privileged
software to associate a shadow set with entry to kernel
mode via an interrupt vector or exception. The normal
GPRs are logically considered shadow set zero.
The PIC32MX3XX/4XX Family core implements two
sets of registers, the normal GPRs, and one shadow
set. This is indicated by the SRSCtl_HSS field.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 39