PIC32MX440F256H-80I Datasheet, PDF (230/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
10.2.1 DMA CONTROLLER TERMINOLOGY
Event: Any system event that can initiate or abort a
DMA transfer.
Transaction: A single-word transfer (up to 4 bytes),
comprised of read and write operations.
Cell Transfer: The number of bytes transferred when
a DMA channel has a transfer initiated before waiting
for another event (given by the DCHCSIZ register). A
cell transfer comprises one or more transactions.
Block Transfer: Defined as the number of bytes trans-
ferred when a channel is enabled. The number of bytes
is the larger of either DCHxSSIZ or DCHxDSIZ. A block
transfer comprises one or more cell transfers.
10.3 Basic Transfer Mode
Basic Transfer mode transfer features:
• The transfer size is limited to a maximum of 256
bytes transferred per channel.
• The Source and Destination Pointers wrap around
based on the selected source and destination
size.
• A block transfer is complete when the block size
bytes have been transferred. The block size is the
larger of source and destination sizes:
- blockSize = max (DCHxSSIZ, DCHxDSIZ).
• A DMA event will transfer cell size (DCHxCSIZ)
bytes from source to destination. However, if
DCHxCSIZ is greater than the block size, then
just block size bytes will be transferred.
10.3.1 BASIC TRANSFER MODE
CONFIGURATION
Microchip recommends taking the following steps to
configure a DMA transfer:
• Disable the DMA channel interrupts in the INT
controller.
• Clear any existing channel interrupt flags in the
INT controller.
• Enable the DMA controller (if not already
enabled) in DMACON register.
• Set Channel Control register: Priority,
Auto-Enable mode, etc., in DCHxCON. (Don’t
enable the channel yet!)
• Set the channel event control: clear/set the events
starting and aborting the transfer. If needed, also
set the pattern match enable in DCHxECON.
• If using a pattern match, set the pattern in the
DCHxDAT register.
• Set the transfer source and destination physical
addresses (DCHxSSA and DCHxDSA registers).
• Set the source and destination sizes (DCHxSSIZ,
DCHxDSIZ registers).
• Set the cell transfer size (DCHxCSIZ).
• Clear any existing event flag in the DCHxINT
register.
• If using interrupts:
- Set the conditions that will generate an inter-
rupt in the DCHxINT register (at least error
interrupt enable and abort interrupt enable,
usually block complete interrupt).
- Set the DMA channel interrupt priority and
subpriority in the INT controller.
- Enable the DMA channel interrupt in the INT
controller.
• Enable the selected DMA channel with CHEN
(DCHxCON<7>).
• If not using system events to start the DMA
transfer use CFORCE (DCHxECON<7>) to start
transfer.
• Until the DMA transfer is complete you can do
some other processing.
• If transfer complete interrupts (cell complete,
block complete, etc.) are enabled, a notification
will be presented in the ISR that the DMA transfer
completed.
• Otherwise, the DMA channel can be polled to see
if the transfer is completed using, for example,
CHBCIF (DCHxINT<3>).
Refer to Example 10-1.
DS61143E-page 228
Preliminary
© 2008 Microchip Technology Inc.