PIC32MX440F256H-80I Datasheet, PDF (77/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

4.2.1.4.1 PLL Lock Status
The LOCK bit (OSCCON<5>) is a read-only Status bit
that indicates the lock status of the PLL. It is automati-
cally set after the typical time delay for the PLL to
achieve lock, also designated as TLOCK. If the PLL
does not stabilize properly during start-up, LOCK may
not reflect the actual status of PLL lock, nor does it
detect when the PLL loses lock during normal opera-
tion.
The LOCK bit is cleared at a Power-on Reset and on
clock switches when the PLL is selected as a destina-
tion clock source. It remains clear when any clock
source not using the PLL is selected.
Refer to the Electrical Characteristics section in the
specific device data sheet for further information on the
PLL lock interval.
4.2.1.4.2 USB PLL Lock Status
The ULOCK bit (OSCCON<6>) is a read-only status bit
that indicates the lock status of the USB PLL. It is auto-
matically set after the typical time delay for the PLL to
achieve lock, also designated as TLOCK. If the PLL
does not stabilize properly during start-up, LOCK may
not reflect the actual status of PLL lock, nor does it
detect when the PLL loses lock during normal opera-
tion.
The ULOCK bit is cleared at a Power-on Reset. It
remains clear when any clock source not using the PLL
is selected.
Refer to the Electrical Characteristics section in the
specific device data sheet for further information on the
PLL lock interval.
4.2.1.4.3 Primary Oscillator Start-up from Sleep
Mode
To ensure reliable wake-up from Sleep, care must be
taken to properly design the primary oscillator circuit.
This is because the load capacitors have both partially
charged to some quiescent value and phase differential
at wake-up is minimal. Thus, more time is required to
achieve stable oscillation. Remember also that low-
voltage, high temperatures and the lower frequency
clock modes also impose limitations on loop gain,
which in turn, affects start-up.
Each of the following factors increases the start-up
time:
• Low-frequency design (with a Low Gain Clock
mode)
• Quiet environment (such as a battery operated
device)
• Operating in a shielded box (away from the noisy
RF area)
• Low voltage
• High temperature
• Wake-up from Sleep mode
PIC32MX3XX/4XX
4.2.1.5 Secondary Oscillator (SOSC)
The Secondary Oscillator (SOSC) is designed specifi-
cally for low-power operation with a external
32.768 kHz crystal. The oscillator is located on the
SOSCO and SOSCI device pins and serves as a sec-
ondary crystal clock source for low-power operation. It
can also drive Timer1 and/or the Real-Time Clock/Cal-
endar module for Real-Time Clock applications.
4.2.1.5.1 Enabling the SOSC Oscillator
The SOSC is hardware enabled by the FSOSCEN
Configuration bit (DEVCFG1<5>). Once SOSC is
enabled, software can control it by modifying SOSCEN
bit (OSCCON<1>). Setting SOSCEN enables the oscil-
lator; the SOSCO and SOSCI pins are controlled by the
oscillator and cannot be used for port I/O or other func-
tions.
Note:
An unlock sequence is required before a
write to OSCCON can occur. Refer to
Section 4.2.6.2 “Oscillator Switching
Sequence” for more information.
The Secondary Oscillator requires a warm-up period
before it can be used as a clock source. When the oscil-
lator is enabled, a warm-up counter increments to
1024. When the counter expires the SOSCRDY
(OSCCON<22>) is set to ‘1’.
4.2.1.5.2 SOSC Continuous Operation
The SOSC is always enabled when SOSCEN
(OSCCON<1>) is set. Leaving the oscillator running at
all times allows a fast switch to the 32 kHz system clock
for lower power operation. Returning to the faster main
oscillator will still require an oscillator start-up time if it
is a crystal type source and/or uses the PLL.
In addition, the oscillator will need to remain running at
all times for Real-Time Clock applications and may be
required for Timer1.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 75