PIC32MX440F256H-80I Datasheet, PDF (39/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
2.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (kernel, user, and debug), and
whether interrupts are enabled or disabled.
Configuration information, such as presence of options
like MIPS16e, is also available by accessing the CP0
registers, listed in Table 2-2.
TABLE 2-2: COPROCESSOR 0 REGISTERS
Register Register
Number Name
Function
0-6
7
8
9
10
11
12
12
12
12
13
14
15
15
16
16
16
16
17-22
23
24
25-29
30
31
Note 1:
2:
Reserved
Reserved in the PIC32MX3XX/4XX Family core
HWREna
BadVAddr⁽¹⁾
Count⁽¹⁾
Enables access via the RDHWR instruction to selected hardware registers
Reports the address for the most recent address-related exception
Processor cycle count
Reserved
Compare⁽¹⁾
Status⁽¹⁾
IntCtl⁽¹⁾
SRSCtl⁽¹⁾
SRSMap⁽¹⁾
Cause⁽¹⁾
EPC⁽¹⁾
Reserved in the PIC32MX3XX/4XX Family core
Timer interrupt control
Processor status and control
Interrupt system status and control
Shadow register set status and control
Provides mapping from vectored interrupt to a shadow set
Cause of last general exception
Program counter at last exception
PRId
Processor identification and revision
EBASE
Exception vector base register
Config
Configuration register
Config1
Configuration register 1
Config2
Configuration register 2
Config3
Configuration register 3
Reserved
Debug⁽²⁾
DEPC⁽²⁾
Reserved in the PIC32MX3XX/4XX Family core
Debug control and exception status
Program counter at last debug exception
Reserved
ErrorEPC⁽¹⁾
DESAVE⁽²⁾
Reserved in the PIC32MX3XX/4XX Family core
Program counter at last error
Debug handler scratchpad register
Registers used in exception processing.
Registers used during debug.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 37