PIC32MX440F256H-80I Datasheet, PDF (45/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
When ERL = 1, useg and kuseg become unmapped
(virtual address is identical to the physical address) and
uncached. This behavior is the same as if there was a
TLB. This mapping is shown in Figure 2-5.
FIGURE 2-5:
PIC32MX3XX/4XX FAMILY CORE FMT MEMORY MAP (ERL = 1)
Virtual Address
kseg3
0xE000_0000
kseg2
0xC000_0000
kseg1
0xA000_0000
kseg0
0x8000_0000
Physical Address
kseg3
0xE000_0000
kseg2
0xC000_0000
reserved
0x8000_0000
useg/kuseg
0x0000_0000
useg/kuseg
kseg0/kseg1
0x0000_0000
2.3.2 DUAL INTERNAL BUS INTERFACES
The SRAM interface includes dual instruction and data
interfaces.
The dual interface enables independent connection to
instruction and data devices. It yields the highest per-
formance, since the pipeline can generate simultane-
ous I and D requests which are then serviced in
parallel.
The internal buses are connected to the Bus Matrix
unit, which is a switch fabric that provides this parallel
operation.
2.3.3 MIPS16E EXECUTION
When the core is operating in MIPS16e mode,
instruction fetches only require 16 bits of data to be
returned. For improved efficiency, however, the core
will fetch 32 bits of instruction data whenever the
address is word-aligned. Thus for sequential MIPS16e
code, fetches only occur for every other instruction,
resulting in better performance and reduced system
power.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 43