PIC32MX440F256H-80I Datasheet, PDF (46/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
2.4 Power Management
The PIC32MX3XX/4XX Family core offers a number of
power management features, including low-power
design, active power management, and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during idle periods.
2.4.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking power-down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 23.0
“Power Saving”.
2.4.2 LOCAL CLOCK GATING
The majority of the power consumed by the
PIC32MX3XX/4XX Family core is in the clock tree and
clocking registers. The PIC32MX family uses extensive
use of local gated-clocks to reduce this dynamic power
consumption.
2.5 EJTAG Debug Support
The PIC32MX3XX/4XX Family core provides for an
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard user mode and kernel modes of
operation, the PIC32MX3XX/4XX Family core provides
a Debug mode that is entered after a debug exception
(derived from a hardware breakpoint, single-step
exception, etc.) is taken and continues until a debug
exception return (DERET) instruction is executed.
During this time, the processor executes the debug
exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring test data in and out of the
PIC32MX3XX/4XX Family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define what
registers are selected and how they are used.
2.5.1 DEBUG REGISTERS
Three debug registers (DEBUG, DEPC, and DESAVE)
have been added to the MIPS Coprocessor 0 (CP0)
register set. The DEBUG register shows the cause of
the debug exception and is used for setting up single-
step operations. The DEPC, or Debug Exception
Program Counter, register holds the address on which
the debug exception was taken. This is used to resume
program execution after the debug operation finishes.
Finally, the DESAVE, or Debug Exception Save,
register enables the saving of general purpose
registers used during execution of the debug exception
handler.
To exit debug mode, a Debug Exception Return
(DERET) instruction is executed. When this instruction
is executed, the system exits debug mode, allowing
normal execution of application and system code to
resume.
2.5.2 EJTAG HARDWARE BREAKPOINTS
There are several types of simple hardware
breakpoints defined in the EJTAG specification. These
stop the normal operation of the MCU and force the
system into debug mode. There are two types of simple
hardware breakpoints implemented in the
PIC32MX3XX/4XX Family core: Instruction
breakpoints and Data breakpoints.
The PIC32MX3XX/4XX Family core has two data and
six instruction breakpoints
Instruction breaks occur on instruction fetch
operations, and the break is set on the virtual address.
A mask can be applied to the virtual address to set
breakpoints on a range of instructions.
Data breakpoints occur on load/store transactions.
Breakpoints are set on virtual address values, similar to
the Instruction breakpoint. Data breakpoints can be set
on a load, a store, or both. Data breakpoints can also
be set based on the value of the load/store operation.
Finally, masks can be applied to both the virtual
address and the load/store value.
2.5.3 INSTRUCTION TRACING
The PIC32MX3XX/4XX Family core includes Trace
support for real-time tracing of instruction addresses.
The trace information is collected in an off-chip
memory, for post-capture processing by trace
regeneration software.
Off-chip trace memory is accessed through a special
trace probe that consists of 4 data pins plus a clock.
DS61143E-page 44
Preliminary
© 2008 Microchip Technology Inc.