PIC32MX440F256H-80I Datasheet, PDF (195/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
9.3 Prefetch Configuration
The CHECON register controls the configurations
available for instruction and data caching of Program
Flash Memory.
In addition to normal instruction caching, the prefetch
cache has the ability to cache lines specifically for
Flash Memory data.
The CHECON.DCSZ field controls the number of lines
allocated to program data caching. Table 9-2 shows
the cache line relationship for values of DCSZ. The
data caching capability is for read only data such as
constants, parameters, table data, etc., that are not
modified.
TABLE 9-2: PROGRAM DATA CACHE
DCSZ<1:0> Lines Allocated to Program Data
00
None
01
Cache Line Number 15
10
Cache Line Number 14 and 15
11
Cache Line Number 12 through 15
The CHECON.PREFEN field controls predictive
prefetching, which allows the prefetch module to spec-
ulatively fetch the next 16-byte aligned set of instruc-
tions.
The prefetch module loads data into the data array only
on accesses to cacheable regions (CCA bits = 3).
EXAMPLE 9-1: EXAMPLE CODE: INITIALIZATION CODE FOR PREFETCH MODULE
/* Prefetch Cache Initialization */
tmp = _CP0_GET_CONFIG();
tmp |= 1;
_CP0_SET_CONFIG(tmp);
// read CONFIG register
// kseg0 cacheable
// write CONFIG register
CHECON = (1<<4) | 3;
// 3 wait-states,
// Prefetching enabled for cached memory
9.3.1 LINE LOCKING
Each line in the cache can be locked to hold its con-
tents. A line is locked if both LVALID = 1 and
LLOCK = 1. If LVALID = 0 and LLOCK = 1, the
prefetch module issues a preload request (see below).
Locking cache lines may reduce the performance of
general program flow. However, if one or two functions
calls consume a significant percent of overall process-
ing, locking their address can provide improved perfor-
mance.
Though any number of lines can be locked, the cache
works most efficiently when locking either 1 or 4 lines.
If locking 4 lines, choose lines whose line number
divide by 4 have the same quotient. This locks an
entire LRU group which benefits the LRU algorithm.
For example, lines 8, 9, A, and B each have a quotient
of 2 when divided by 4.
If cache lines are manually filled, it is recommended
that the following sequence be used:
1. Choose a cache line to fill.
2. Set the Lock and Valid bits of the cache line by
writing to CHETAG.
3. Write to each word of the cache line by writing to
CHEW0, CHEW1, CHEW2, and CHEW3.
EXAMPLE 9-2: EXAMPLE CODE: LOCKING A LINE IN PREFETCH MODULE
#define LOCKED_LINE_NUM 3
/* lock first line of func1() in cache */
CHEACC = (1<<31) | LOCKED_LINE_NUM;
tmp = (unsigned long)func1;
ltagboot = (tmp & 0x00c00000) ? 0 : 1;
CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0) | 6;
// locked and invalid
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 193