PIC32MX440F256H-80I Datasheet, PDF (215/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 10-7: DCHXCON: DMA CHANNEL X CONTROL REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
bit 31
r-x
—
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
bit 16
r-x
—
bit 15
r-x
r-x
r-x
r-x
r-x
r-x
R/W-0
—
—
—
—
—
—
CHCHNS
bit 8
R/W-0
CHEN
bit 7
R/W-0
CHAED
R/W-0
CHCHN
R/W-0
CHAEN
r-x
R-0
R/W-0
R/W-0
—
CHEDET
CHPRI<1:0>
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Reserved: Write ‘0’; ignore read
CHCHNS: Chain Channel Selection bit
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
Note: The chain selection bit takes effect when chaining is enabled, i.e., CHCHN = 1.
CHEN: Channel Enable bit
1 = Channel is enabled
0 = Channel is disabled
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained to channel higher in natural priority
0 = Do not chain to channel higher in natural priority
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
Reserved: Write ‘0’; ignore read
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
CHPRI<1:0>: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 213