PIC32MX440F256H-80I Datasheet, PDF (44/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
In the PIC32MX3XX/4XX Family core, no translation
exceptions are taken, although address errors are still
possible.
TABLE 2-5: CACHEABILITY OF SEGMENTS WITH FIXED MAPPING TRANSLATION
Segment
Virtual Address Range
Cacheability
useg/kuseg
kseg0
kseg1
kseg2
kseg3
0x0000_0000-0x7FFF_FFFF
0x8000_0000- 0x9FFF_FFFF
0xA000_0000-0xBFFF_FFFF
0xC000_0000-0xDFFF_FFFF
0xE000_0000-0xFFFF_FFFF
Controlled by the KU field (bits 27:25) of the Config register.
See Figure 2-4 for mapping.
This segment is always uncached when ERL = 1.
Controlled by the K0 field (bits 2:0) of the Config register.
See Figure 2-4 for mapping.
Always uncacheable.
Controlled by the K23 field (bits 30:28) of the Config register.
See Figure 2-4 for mapping.
Controlled by the K23 field (bits 30:28) of the Config register.
See Figure 2-4 for mapping.
The FMT performs a simple translation to map from
virtual addresses to physical addresses. This mapping
is shown in Figure 2-4.
FIGURE 2-4:
FMT MEMORY MAP (ERL = 0) IN THE PIC32MX3XX/4XX FAMILY CORE
Virtual Address
kseg3
0xE000_0000
kseg2
0xC000_0000
kseg1
0xA000_0000
kseg0
0x8000_0000
Physical Address
kseg3
0xE000_0000
kseg2
0xC000_0000
useg/kuseg
useg/kuseg
0x0000_0000
0x4000_0000
reserved
0x2000_0000
kseg0/kseg1
0x0000_0000
DS61143E-page 42
Preliminary
© 2008 Microchip Technology Inc.