PIC32MX440F256H-80I Datasheet, PDF (324/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
12.2 Parallel I/O (PIO) Ports
All port pins have three registers (TRIS, LAT, and
PORT) that are directly associated with their operation.
TRIS is a data direction or tri-state control register that
determines whether a digital pin is an input or an out-
put. Setting a TRISx register bit = 1 configures the cor-
responding I/O pin as an input; setting a TRISx register
bit = 0 configures the corresponding I/O pin as an out-
put. All port I/O pins are defined as inputs after a device
Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx regis-
ter, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx latch
register reads the last value written to the
corresponding port or latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros. See Section 12.1
“Port Registers”.
12.2.1 CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
To set PORTC bit 0, write to the LATSET register:
LATCSET = 0x0001;
To clear PORTC bit 0, write to the LATCLR register:
LATCCLR = 0x0001;
To toggle PORTC bit 0, write to the LATINV register:
LATCINV = 0x0001;
Note:
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions as compared to the tra-
ditional read-modify-write method shown
below:
PORTC ^= 0x0001;
12.2.2 DIGITAL INPUTS
Pins are configured as digital inputs by setting the cor-
responding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
Several digital pins share functionality with analog
inputs and default to the analog inputs at POR. Setting
the corresponding bit in the ADP1CFG register = 1
enables the pin as a digital pin.
Digital only pins are capable of input voltages up to
5.5V. Any pin that shares digital and analog
functionality is limited to voltages up to VDD + 0.3V.
.
TABLE 12-10: MAXIMUM INPUT PIN
VOLTAGES
Input Pin Mode(s)
VIH (max)
Digital Only
Digital + Analog
Analog
VIH = 5.5v
VIH = VDD + 0.03v
VIH = VDD + 0.03v
Note: Refer to Section 30.0 “Electrical Characteris-
tics” regarding the VIH specification.
Note:
Analog levels on any pin that is defined as
a digital input (including the ANx pins) may
cause the input buffer to consume current
that exceeds the device specifications.
12.2.3 ANALOG INPUTS
Certain pins can be configured as analog inputs used
by the ADC and Comparator modules. Setting the cor-
responding bits in the ADP1CFG register = 0 enables
the pin as an analog input pin and must have the corre-
sponding TRIS bit set = 1 (input). If the TRIS bit is
cleared = 0 (output), the digital output level (VOH or
VOL) will be converted. Any time a port I/O pin is config-
ured as analog, its digital input is disabled and the cor-
responding PORTx register bit will read ‘0’.
12.2.4 DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the cor-
responding TRIS register bits = 0. When configured as
digital outputs, these pins are CMOS drivers or can be
configured as open drain outputs by setting the corre-
sponding bits in the ODCx Open-Drain Configuration
register.
Digital output pin voltage is limited to VDD.
12.2.5 ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such
as the CVREF output voltage used by the comparator
module. Configuring the Comparator Reference mod-
ule to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
DS61143E - page 322
Preliminary
© 2008 Microchip Technology Inc.