PIC32MX440F256H-80I Datasheet, PDF (169/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

8.2 Operation
The interrupt controller is responsible for pre-
processing Interrupt Requests (IRQ) from a number of
on-chip peripherals and presenting them in the
appropriate order to the processor.
Figure 8-2 depicts the process within the interrupt con-
troller module. The interrupt controller is designed to
receive up to 96 IRQs from the processor core and
from on-chip peripherals capable of generating inter-
rupts. All IRQs are sampled on the rising edge of the
SYSCLK and latched in associated IFSx registers. A
pending IRQ is indicated by the flag bit being equal to
‘1’ in an IFSx register. The pending IRQ will not cause
further processing if the corresponding bit in the Inter-
rupt Enable (IECx) register is clear. The IECx bits act to
gate the interrupt flag. If the interrupt is enabled, all
IRQs are encoded into a 5-bit wide vector number. The
5-bit vector results in 0 to 63 unique interrupt vector
numbers. Since there are more IRQs than available
vector numbers, some IRQs share common vector
numbers. Each vector number is assigned an interrupt
priority level and shadow set number. The priority level
is determined by the IPCx register setting of the asso-
ciated vector. In Multi-Vector mode, all priority level 7
interrupts use a dedicated register set, while in Single
Vector mode, all interrupts may receive a dedicated
shadow set. The interrupt controller selects the highest
priority IRQ among all pending IRQs and presents the
associated vector number, priority level and shadow
set number to the processor core.
The processor core samples the presented vector
information between the ‘E’ and ‘M’ stage of the pipe-
line. If the vector’s priority level presented to the core is
greater than the current priority indicated by the CPU
Interrupt Priority bits IPLx (Status<15:10>), the inter-
rupt is serviced; otherwise, it will remain pending until
the current priority is less than the interrupt’s priority.
When servicing an interrupt, the processor core pushes
the program counter into the Exception Program Coun-
ter (EPC) register in the CPU and sets Exception Level
bit EXL (Status<1>) in the CPU. The EXL bit disables
further interrupts until the application explicitly re-
enables them by clearing the EXL bit. Next, it branches
to the vector address calculated from the presented
vector number.
PIC32MX3XX/4XX
The INTSTAT register contains the Interrupt Vector
Number bits, VEC (INTSTAT<5:0>), and Requested
Interrupt Priority bits, RIPLx (INTSTAT<10:8>), of the
current pending interrupt. This may not be the same as
the interrupt which caused the core to diverge from
normal execution.
The processor returns to the previous state when the
ERET (Exception Return) instruction is executed. ERET
clears the EXL bit, restores the program counter and
reverts the current shadow set to the previous one.
The PIC32MX3XX/4XX interrupt controller can be con-
figured to operate in one of two modes:
• Single Vector mode – all interrupt requests will be
serviced at one vector address (mode out of
Reset).
• Multi-Vector mode – interrupt requests will be
serviced at the calculated vector address.
Notes:
While the user can, during run time,
reconfigure the interrupt controller from
Single Vector to Multi-Vector mode (or
vice versa), such action is strongly dis-
couraged. Changing interrupt controller
modes after initialization may result in
undefined behavior.
The M4K core supports several different
interrupt processing modes. The interrupt
controller is designed to work in External
Interrupt Controller mode.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 167