PIC32MX440F256H-80I Datasheet, PDF (414/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
18.11 Slope Control
The I²C standard requires slope control on the SDAx
and SCLx signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate
control if desired. It is necessary to disable the slew
rate control for 1 MHz mode.
18.12 Clock Arbitration
Clock arbitration occurs when the master deasserts the
SCLx pin (SCLx allowed to go high by external pull-up
resistors) during any receive, transmit or Restart/Stop
condition. When the SCLx pin is allowed to float high,
the Baud Rate Generator (BRG) is suspended from
counting until the SCLx pin is actually sampled high.
When the SCLx pin is sampled high, the Baud Rate
Generator is reloaded with the contents of I2CxBRG
and begins counting. This ensures that the SCLx high
time will always be at least one BRG rollover count in
the event that the clock is held low by an external
device.
18.13 Multi-Master Communication, Bus
Collision and Bus Arbitration
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx by letting SDAx float high
while another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the
SDAx pin = 0, then a bus collision has taken place. The
master will set the I²C master events interrupt flag and
reset the master portion of the I²C port to its Idle state.
FIGURE 18-2:
TYPICAL I²C™ INTERCONNECTION BLOCK DIAGRAM
PIC32MX3XX/4XX
SCLX
SDAX
VDD VDD
4.7 kΩ
(typical)
24LC256
SCL
SDA
DS61143E-page 412
Preliminary
© 2008 Microchip Technology Inc.