PIC32MX440F256H-80I Datasheet, PDF (38/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
TABLE 2-1: PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
Operand Size (mul rt) (div rs)
Latency
MULT/MULTU, MADD/MADDU,
16 bits
1
MSUB/MSUBU
32 bits
2
MUL
16 bits
2
32 bits
3
DIV/DIVU
8 bits
12
16 bits
19
24 bits
26
32 bits
33
Repeat Rate
1
2
1
2
11
18
25
32
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the general purpose register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, multiply-add (MADD) and
multiply-subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
DS61143E-page 36
Preliminary
© 2008 Microchip Technology Inc.