PIC32MX440F256H-80I Datasheet, PDF (406/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
17.2.4.12 Framed Slave Mode Initialization
The following steps are used to set up the SPI module
for the Slave mode of operation:
1. If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
2. Stop and reset the SPI module by clearing the
ON bit.
3. Clear the receive buffer.
4. If using interrupts, the following additional steps
are performed:
• Clear the SPIx interrupt flags/events in the
respective IFS0/1 register.
• Set the SPIx interrupt enable bits in the
respective IEC0/1 register.
• Write the SPIx interrupt priority and
subpriority bits in the respective IPC5/7
register.
5. Clear the SPIROV bit (SPIxSTAT<6>).
6. Write the selected configuration settings to the
SPIxCON register.
7. Enable SPI operation by setting the ON bit
(SPIxCON<15>).
8. Transmission (and reception) will start as soon
as the master provides the serial clock.
Note 1: The user must turn off the SPI device
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
2: The SPIxSR register cannot be written
into directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
3: Receiving a frame sync pulse will start a
transmission, regardless of whether or
not data was written to SPIxBUF. If a
write was not performed, zeros will be
transmitted.
FIGURE 17-10: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC32MX3XX/4XX
[SPI Slave, Frame Slave]
SDOx
PROCESSOR 2
[SPI Master, Frame Master]
SDIx
SDIx
SCKx
SSx
Serial Clock
SDOx
SCKx
SSx
Frame Sync
Pulse^(1)(2)(3)
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse.
2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).
3: Slave Select is not available when using Frame mode as a slave device.
DS61143E-page 404
Preliminary
© 2008 Microchip Technology Inc.