PIC32MX440F256H-80I Datasheet, PDF (447/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 9-8
bit 7-6
MODE1:MODE0: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<15:0>)^(3,4)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<15:0>)^(3,4)
01 = Addressable Slave Mode, control signals (PMRD, PMWR, PMCS, PMD<7:0>, PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS, PMD<7:0>)
WAITB1:WAITB0: Data Setup to Read/Write Strobe Wait States bits⁽¹⁾
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB
01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (DEFAULT)
bit 5-2
WAITM3:WAITM0: Data Read/Write Strobe Wait States bits
bit 1-0
1111 = Wait of 16 TPB
...
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (DEFAULT)
WAITE1:WAITE0: Data Hold After Read/Write Strobe Wait States bits⁽¹⁾
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (DEFAULT)
Note 1:
2:
3:
4:
5:
for Read operations:
11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
00 = Wait of 0 TPB (DEFAULT)
Whenever WAITM3:WAITM0 = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
When ADDR15 and ADDR14 are used as CS2 and CS1, or ADDR15 is used as CS2, these bits are not
subject to auto-increment/decrement.
In Master Mode 1 or Master Mode 2, data pins PMD<15:0> are active when MODE16 = 1; data pins
PMD<7:0> are active when MODE16 = 0.
On 64-pin devices, data pins PMD<15:8> are not available.
The PMADDR register is always incremented/decremented by 1, regardless of the transfer data width.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 445