PIC32MX440F256H-80I Datasheet, PDF (127/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
8.0 INTERRUPTS
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a
detailed description of this peripheral.
PIC32MX3XX/4XX generates interrupt requests in
response to interrupt events from peripheral modules.
The Interrupt Control Module exists external to the
CPU logic and prioritizes the interrupt events before
presenting them to the CPU.
The PIC32MX3XX/4XX interrupts module includes the
following features:
• Up to 96 interrupt sources
• Up to 64 interrupt vectors
• Single and Multi-Vector mode operations
• 5 external interrupts with edge polarity control
• Interrupt proximity timer
• Module Freeze in Debug mode
• 7 user-selectable priority levels for each vector
• 4 user-selectable subpriority levels within each
priority
• Dedicated shadow set for highest priority level
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
FIGURE 8-1:
INTERRUPT CONTROLLER MODULE
Vector Number
Interrupt Controller
Priority Level
Shadow Set Number
CPU Core
Note:
Several of the registers cited in this section are not in the interrupt controller module. These registers (and
bits) are associated with the CPU. Details about them are available in Section 2.0 "PIC32MX MCU".
To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this
section, and all other sections of this manual, are signified by uppercase letters only.CPU register names
are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas,
IntCtl is a CPU register.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 125