PIC32MX440F256H-80I Datasheet, PDF (337/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

13.4.1 Synchronous Internal Gated Timer
In this mode, the timer clock source can only be the
internal PBCLK (Peripheral Bus Cock), TCS
(T1CON<1>) = 0. The T1CK pin provides the gating
mechanism to enable and disable the timer counting,
TGATE (T1CON<7>) = 1. Clock synchronization is not
required, therefore Timer1 synchronization bit, TSYNC
(T1CON<2>), is ignored. The 16-bit TMR1 Count reg-
ister is enabled on the rising edge of the T1CK pin and
increments on every internal PBCLK cycle when the
timer clock prescale <TCKPS> is 1:1.
The timer increments until the TMR1 Count register
matches the PR1 register value. The TMR1 Count reg-
ister resets to 0x0000 on the next PBCLK clock cycle.
A timer match event is not generated. The timer contin-
ues to increment and repeat the period match until the
falling edge of the T1CK pin or the timer is disabled. On
the falling edge of the gate signal, a timer gate event is
generated and the TMR1 Count register stops count-
ing, but is not reset to 0x0000. The TMR1 Count regis-
ter must be reset in software. For further details
regarding timer events and interrupts, see
Section 13.5 “Timer Interrupts”.
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMR1
Count register increments on every Nth PBCLK clock
cycle. For further details regarding timer prescaler,
refer to Section 13.4.2 “Timer Clock Prescaler”.
The following steps should be performed to properly
configure the Timer1 peripheral for Gated Timer mode
operation:
1. Clear control bit, ON (T1CON<15>) = 0, to
disable Timer1.
2. Select the desired timer prescaler using bits,
TCKPS<1:0> (T1CON<5:4>).
3. Set control bit, TCS (T1CON<1>) = 0, to select
the internal clock source.
4. Set control bit TGATE (T1CON<6>) = 1.
5. Clear Timer register, TMR1.
6. Load Period register, PR1, with desired
16-bit match value.
7. If timer interrupts are used, refer to Section 13.5
“Timer Interrupts” for interrupt configuration
steps.
8. Set control bit ON, (T1CON<15>) = 1, to enable
Timer1.
PIC32MX3XX/4XX
EXAMPLE 13-4:
SYNCHRONOUS
INTERNAL GATED TIMER
INITIALIZATION
T1CON = 0x0;
T1CON = 0x0060;
TMR1 = 0x0;
PR1 = 0xFFFF;
// Stop Timer and reset
// Enable gated mode,
// prescaler at 1:64,
// internal clock source
// Clear timer register
// Load period register
T1CONSET = 0x8000;// Start Timer
13.4.2 TIMER CLOCK PRESCALER
Timer clock prescale bits, TCKPS<1:0>
(T1CON<5:4>), are used to divide the timer clock
source, permitting the TMR register to increment on
every 1, 8, 64, or 256 (PBCLK or external) clock cycles.
For example, if the clock prescale is 1:8, then the timer
increments on every 8th timer clock cycle.
Associated with the clock prescale selection bits is a
prescale counter. This prescale counter is cleared
when any of the following conditions occur:
• Any device Reset, except a Power-on Reset
• The timer is disabled
• A write to the TMR register
Note:
When the timer clock source is external
and the timer clock prescale = N (other
than 1:1), 2 to 3 external clock cycles are
required to reset and synchronize the
prescaler.
• When the timer clock source is external and the
timer clock prescale = N (other than 1:1), 2 to 3
external clock cycles are required, after the timer
ON bit is set = 1, before the TMR1 Count register
increments.
• After a timer match event (TMR1 = PR1) and
depending on the timer clock prescale setting N
(other than 1:1), the timer will require N/2 addi-
tional (PBCLK or external) clock cycles before the
TMR1 Counter register reset to 0x0000. Reading
the TMR1 Count register just after the timer match
event, but before the TMR1 Count register is rest,
will return the timer match value.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 335