PIC32MX440F256H-80I Datasheet, PDF (405/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
FIGURE 17-9:
SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC32MX3XX/4XX
[SPI Slave, Frame Master]
SDOx
PROCESSOR 2
[SPI Master, Frame Slave]
SDIx
SDIx
SCKx
Serial Clock
SDOx
SCKx
SSx
SSx
Frame Sync
Pulse⁽¹⁾⁽²⁾
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse.
2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).
17.2.4.10 SPI Slave Mode and Frame Slave
Mode
This Framed SPI mode is enabled by setting bits
MSTEN (SPIxCON<5>) to ‘0’, FRMEN
(SPIxCON<31>) to ‘1’, and FRMSYNC
(SPIxCON<30>) to ‘1’. Therefore, both the SCKx and
SSx pins will be inputs. The SSx pin will be sampled on
the sample edge of the SPI clock. When SSx is sam-
pled active, high or low depending on bit, FRMPOL
(SPIxCON<29>), data will be transmitted on the next
transmit edge of SCKx. A connection diagram
indicating signal directions for this operating mode is
shown in Figure 17-10.
The SDO pins is an output and the SCK, SDI and SSx
pins are inputs. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired; refer to
Table 17-7.
The SDI pin must be configured to properly sample the
data received from the slave device by configuring the
sample bit, SMP (SPIxCON<9>).
Refer to timing diagram shown in Figure 17-7 to
determine the appropriate settings.
17.2.4.11 Slave SPIxCON Configuration
The following bits must be configured as shown for the
Slave mode of operation when configuring the
SPIxCON register:
• Enable Slave Mode –
MSTEN (SPIxCON<5>) = 0
• Enable Framed SPI support –
FRMEN (SPIxCON<31>) = 1
• Select SSx pin as Frame Slave (input) –
FRMSYNC(SPIxCON<30>) = 1
The remaining bits are shown with example
configurations and may be configured as desired:
• Enable module control of SDO pin –
DISSDO (SPIxCON<12>) = 0
• Configure SCK clock polarity to Idle high –
CKP (SPIxCON<6>) = 1
• Configure SCK clock edge transition from Idle to
active – CKE (SPIxCON<8>) = 0
• Select SSx active-low pin polarity –
FRMPOL (SPIxCON<29>) = 0
• Select 16-bit data width –
MODE<32,16> (SPIxCON<11:10>) = ‘01’
• Sample data input at middle –
SMP (SPIxCON<9>) = 0
• Enable SPI module when CPU Idle –
SIDL (SPIxCON<13>) = 0
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 403