PIC32MX440F256H-80I Datasheet, PDF (240/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
10.10 DMA Interrupts
The DMA device has the ability to generate interrupts
reflecting the events that occur during the channel’s
data transfer. The different kinds of DMA interrupt flags
are:
• CHERIF (DCHxINT<0>): Channel Error
interrupts, enabled using CHERIE
(DCHxINT<16>).
• CHTAIF (DCHxINT<1>): Channel Abort interrupts,
enabled using CHTAIE (DCHxINT<17>).
• CHBCIF (DCHxINT<3>): Channel Block complete
interrupts, enabled using CHBCIE
(DCHxINT<19>).
• CHCCIF (DCHxINT<2>): Channel Cell complete
interrupts, enabled using CHCCIE
(DCHxINT<18>).
• CHSDIF (DCHxINT<7>): Channel Source pointer
reached the end of the source, enabled by
CHSDIE (DCHxINT<23>).
• CHSHIF (DCHxINT<6>): Channel Source pointer
reached midpoint of the source, enabled by
CHSHIE (DCHxINT<22>).
• CHDDIF (DCHxINT<5>): Channel Destination
Pointer reached the end of the destination,
enabled by CHDDIE (DCHxINT<21>)
• CHDHIF (DCHxINT<4>): Channel Destination
Pointer reached midpoint of the destination,
enabled by CHDHIE (DCHxINT<20>).
All the interrupts belonging to a DMA channel map to
the corresponding channel interrupt vector.
The corresponding interrupt flags are:
• DMA0IF (IFS1<16>)
• DMA1IF (IFS1<17>)
• DMA2IF (IFS1<18>)
• DMA3IF (IFS1<19>)
All these interrupt flags must be cleared in software.
A DMA channel is enabled as a source of interrupts via
the respective DMA interrupt enable bits:
• DMA0IE (IEC1<16>)
• DMA1IE (IEC1<17>)
• DMA2IE (IEC1<18>)
• DMA3IE (IEC1<19>)
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• DMA0IP<2:0> (IPC9<4:2>), DMA0IS<1:0>
(IPC9<1:0>).
• DMA1IP<2:0> (IPC9<12:10>), DMA1IS<1:0>
(IPC9<9:8>).
• DMA2IP<2:0> (IPC9<20:18>), DMA2IS<1:0>
(IPC9<17:16>).
• DMA3IP<2:0> (IPC9<28:26>), DMA3IS<1:0>
(IPC9<25:24>).
In addition to enabling the DMA interrupts, Interrupt
Service Routines (ISRs) are required for each different
interrupt vector used. See Example 10-6 and
Example 10-7.
Note:
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
DS61143E-page 238
Preliminary
© 2008 Microchip Technology Inc.