PIC32MX440F256H-80I Datasheet, PDF (419/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 18-2: I2CXSTAT: I²C STATUS REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
bit 16
R-0
R-0
r-x
r-x
r-x
R/W-0
R-0
R-0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
bit 15
bit 8
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R-0
IWCOL
I2COV
D/A
P
S
R/W
bit 7
R-0
RBF
R-0
TBF
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-16
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
Reserved: Write ‘0’; ignore read
ACKSTAT: Acknowledge Status bit
In both I²C Master and Slave modes; applicable to both transmit and receive.
1 = Acknowledge was not received
0 = Acknowledge was received
TRSTAT: Transmit Status bit
In I²C Master mode only; applicable to Master Transmit mode.
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Reserved: Write ‘0’; ignore read
BCL: Master Bus Collision Detect bit
Cleared when the I²C module is disabled (ON = 0).
1 = A bus collision has been detected during a master operation
0 = No collision has been detected
GCSTAT: General Call Status bit
Cleared after Stop detection.
1 = General call address was received
0 = General call address was not received
ADD10: 10-bit Address Status bit
Cleared after Stop detection.
1 = 10-bit address was matched
0 = 10-bit address was not matched
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register collided because the I²C module is busy.
Must be cleared in software.
0 = No collision
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 417